| /external/llvm/lib/Transforms/ObjCARC/ |
| D | PtrState.h | 113 RRInfo RRI; variable
118 bool IsKnownSafe() const { return RRI.KnownSafe; } in IsKnownSafe()
120 void SetKnownSafe(const bool NewValue) { RRI.KnownSafe = NewValue; } in SetKnownSafe()
122 bool IsTailCallRelease() const { return RRI.IsTailCallRelease; } in IsTailCallRelease()
125 RRI.IsTailCallRelease = NewValue; in SetTailCallRelease()
129 return RRI.ReleaseMetadata != nullptr; in IsTrackingImpreciseReleases()
132 const MDNode *GetReleaseMetadata() const { return RRI.ReleaseMetadata; } in GetReleaseMetadata()
134 void SetReleaseMetadata(MDNode *NewValue) { RRI.ReleaseMetadata = NewValue; } in SetReleaseMetadata()
136 bool IsCFGHazardAfflicted() const { return RRI.CFGHazardAfflicted; } in IsCFGHazardAfflicted()
139 RRI.CFGHazardAfflicted = NewValue; in SetCFGHazardAfflicted()
[all …]
|
| D | PtrState.cpp | 135 RRI.clear(); in ResetSequenceProgress()
145 RRI.clear(); in Merge()
157 Partial = RRI.Merge(Other.RRI); in Merge()
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 651 MCRegUnitRootIterator RRI; variable
660 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) { in MCRegAliasIterator()
661 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) { in MCRegAliasIterator()
681 ++RRI; in advance()
682 if (RRI.isValid()) { in advance()
683 SI = MCSuperRegIterator(*RRI, MCRI, true); in advance()
689 RRI = MCRegUnitRootIterator(*RI, MCRI); in advance()
690 SI = MCSuperRegIterator(*RRI, MCRI, true); in advance()
|
| /external/clang/test/CXX/dcl.decl/dcl.meaning/dcl.ref/ |
| D | p6-0x.cpp | 19 typedef int&& RRI; typedef
25 typedef RRI& r4; CHECK_EQUAL_TYPES(r4, int&);
26 typedef RRI&& r5; CHECK_EQUAL_TYPES(r5, int&&);
|
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| D | ObjCARC.cpp | 1206 RRInfo RRI; member in __anon2a2b45350811::PtrState
1245 RRI.ReleaseMetadata = M; in SetSeqToRelease()
1246 } else if (Seq != S_MovableRelease || RRI.ReleaseMetadata != M) { in SetSeqToRelease()
1248 RRI.ReleaseMetadata = 0; in SetSeqToRelease()
1258 RRI.clear(); in ClearSequenceProgress()
1272 if (RRI.IsRetainBlock != Other.RRI.IsRetainBlock) in Merge()
1276 RRI.clear(); in Merge()
1279 if (RRI.ReleaseMetadata != Other.RRI.ReleaseMetadata) in Merge()
1280 RRI.ReleaseMetadata = 0; in Merge()
1282 RRI.KnownSafe = RRI.KnownSafe && Other.RRI.KnownSafe; in Merge()
[all …]
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | InductiveRangeCheckElimination.cpp | 557 const LoopConstrainer::RewrittenRangeInfo &RRI) const;
1021 RewrittenRangeInfo RRI; in changeIterationSpaceEnd() local
1024 RRI.ExitSelector = BasicBlock::Create(Ctx, Twine(LS.Tag) + ".exit.selector", in changeIterationSpaceEnd()
1026 RRI.PseudoExit = BasicBlock::Create(Ctx, Twine(LS.Tag) + ".pseudo.exit", &F, in changeIterationSpaceEnd()
1039 B.CreateCondBr(EnterLoopCond, LS.Header, RRI.PseudoExit); in changeIterationSpaceEnd()
1042 LS.LatchBr->setSuccessor(LS.LatchBrExitIdx, RRI.ExitSelector); in changeIterationSpaceEnd()
1053 B.SetInsertPoint(RRI.ExitSelector); in changeIterationSpaceEnd()
1061 B.CreateCondBr(IterationsLeft, RRI.PseudoExit, LS.LatchExit); in changeIterationSpaceEnd()
1064 BranchInst::Create(ContinuationBlock, RRI.PseudoExit); in changeIterationSpaceEnd()
1080 RRI.ExitSelector); in changeIterationSpaceEnd()
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
271 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
503 // Format EXT-RRI instruction class in Mips16 :
528 // Format EXT-RRI-A instruction class in Mips16 :
529 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
|
| D | Mips16InstrInfo.td | 231 // EXT-RRI instruction format
246 // EXT-RRI-A instruction format
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 192 def MOV32rr : RRI<0x18,
526 def NEG32rr : RRI<0x13,
546 def ADD32rr : RRI<0x1A, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
592 def ADC32rr : RRI<0x1E, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
621 def AND32rr : RRI<0x14,
685 def OR32rr : RRI<0x16,
748 def SUB32rr : RRI<0x1B,
770 def SBC32rr : RRI<0x1F,
800 def XOR32rr : RRI<0x17,
841 def MUL64rrP : RRI<0x1C,
[all …]
|
| D | SystemZInstrFormats.td | 84 class RRI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
|