Searched refs:RegIndex (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| D | PTXInstPrinter.cpp | 60 int RegIndex; in printPredicate() local
64 RegIndex = 0; in printPredicate()
67 RegIndex = MI->getNumOperands()-2; in printPredicate()
80 printOperand(MI, RegIndex, O); in printPredicate()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | ExecutionDepsFix.cpp | 139 int RegIndex(unsigned Reg);
163 int ExeDepsFix::RegIndex(unsigned Reg) { in RegIndex() function in ExeDepsFix
278 int rx = RegIndex(*i); in enterBasicBlock()
317 int rx = RegIndex(mo.getReg()); in visitHardInstr()
326 int rx = RegIndex(mo.getReg()); in visitHardInstr()
346 int rx = RegIndex(mo.getReg()); in visitSoftInstr()
430 int rx = RegIndex(mo.getReg()); in visitSoftInstr()
444 int rx = RegIndex(mo.getReg()); in visitGenericInstr()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600ISelLowering.cpp | 99 int64_t RegIndex = MI->getOperand(1).getImm(); in EmitInstrWithCustomInserter() local
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex); in EmitInstrWithCustomInserter()
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); in LowerOperation() local
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); in LowerOperation()
282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); in LowerOperation() local
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); in LowerOperation()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 1036 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress() argument
1039 return RegIndex; in calculateIndirectAddress()
1056 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1058 unsigned Address = calculateIndirectAddress(RegIndex, Channel); in expandPostRAPseudo()
1070 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1072 unsigned Address = calculateIndirectAddress(RegIndex, Channel); in expandPostRAPseudo()
1079 calculateIndirectAddress(RegIndex, Channel), in expandPostRAPseudo()
1221 unsigned RegIndex; in getIndirectIndexBegin() local
1223 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; in getIndirectIndexBegin()
1224 ++RegIndex) { in getIndirectIndexBegin()
[all …]
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| D | R600InstrInfo.h | 225 unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
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| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1168 SlotIndex RegIndex = Idx.getRegSlot(); in eliminateUndefCopy() local
1171 VNInfo *VNI = DstLI.getVNInfoAt(RegIndex); in eliminateUndefCopy()
1180 VNInfo *SVNI = SR.getVNInfoAt(RegIndex); in eliminateUndefCopy()
1181 assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex)); in eliminateUndefCopy()
1186 LIS->removeVRegDefAt(DstLI, RegIndex); in eliminateUndefCopy()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 546 void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
3918 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { in warnIfRegIndexIsAT() argument
3919 if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex) in warnIfRegIndexIsAT()
3920 Warning(Loc, "used $at (currently $" + Twine(RegIndex) + in warnIfRegIndexIsAT()
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