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Searched refs:RegNo (Results 1 – 25 of 143) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineRegisterInfo.h104 reg_iterator reg_begin(unsigned RegNo) const { in reg_begin() argument
105 return reg_iterator(getRegUseDefListHead(RegNo)); in reg_begin()
111 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } in reg_empty() argument
116 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { in reg_nodbg_begin() argument
117 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); in reg_nodbg_begin()
123 bool reg_nodbg_empty(unsigned RegNo) const { in reg_nodbg_empty() argument
124 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); in reg_nodbg_empty()
129 def_iterator def_begin(unsigned RegNo) const { in def_begin() argument
130 return def_iterator(getRegUseDefListHead(RegNo)); in def_begin()
136 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } in def_empty() argument
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h79 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { in getRegUseDefListHead() argument
80 if (TargetRegisterInfo::isVirtualRegister(RegNo)) in getRegUseDefListHead()
81 return VRegInfo[RegNo].second; in getRegUseDefListHead()
82 return PhysRegUseDefLists[RegNo]; in getRegUseDefListHead()
85 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { in getRegUseDefListHead() argument
86 if (TargetRegisterInfo::isVirtualRegister(RegNo)) in getRegUseDefListHead()
87 return VRegInfo[RegNo].second; in getRegUseDefListHead()
88 return PhysRegUseDefLists[RegNo]; in getRegUseDefListHead()
247 reg_iterator reg_begin(unsigned RegNo) const { in reg_begin() argument
248 return reg_iterator(getRegUseDefListHead(RegNo)); in reg_begin()
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/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCRegisterInfo.h198 const MCRegisterDesc &operator[](unsigned RegNo) const {
199 assert(RegNo < NumRegs &&
201 return Desc[RegNo];
207 const MCRegisterDesc &get(unsigned RegNo) const { in get() argument
208 return operator[](RegNo); in get()
215 const unsigned *getAliasSet(unsigned RegNo) const { in getAliasSet() argument
217 return get(RegNo).Overlaps + 1; in getAliasSet()
225 const unsigned *getOverlaps(unsigned RegNo) const { in getOverlaps() argument
226 return get(RegNo).Overlaps; in getOverlaps()
234 const unsigned *getSubRegisters(unsigned RegNo) const { in getSubRegisters() argument
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/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp77 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass() argument
79 assert(RegNo < Size && "Invalid register"); in decodeRegisterClass()
80 RegNo = Regs[RegNo]; in decodeRegisterClass()
81 if (RegNo == 0) in decodeRegisterClass()
83 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
87 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR32BitRegisterClass() argument
90 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); in DecodeGR32BitRegisterClass()
93 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGRH32BitRegisterClass() argument
96 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); in DecodeGRH32BitRegisterClass()
99 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGR64BitRegisterClass() argument
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/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmLexer.cpp106 int RegNo = -1; in LexTokenATT() local
108 case '0': RegNo = X86::DR0; break; in LexTokenATT()
109 case '1': RegNo = X86::DR1; break; in LexTokenATT()
110 case '2': RegNo = X86::DR2; break; in LexTokenATT()
111 case '3': RegNo = X86::DR3; break; in LexTokenATT()
112 case '4': RegNo = X86::DR4; break; in LexTokenATT()
113 case '5': RegNo = X86::DR5; break; in LexTokenATT()
114 case '6': RegNo = X86::DR6; break; in LexTokenATT()
115 case '7': RegNo = X86::DR7; break; in LexTokenATT()
118 if (RegNo != -1) { in LexTokenATT()
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DX86AsmParser.cpp88 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
125 unsigned RegNo; member
163 return Reg.RegNo; in getReg()
326 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) { in CreateReg()
328 Res->Reg.RegNo = RegNo; in CreateReg()
392 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo, in ParseRegister() argument
394 RegNo = 0; in ParseRegister()
404 RegNo = MatchRegisterName(Tok.getString()); in ParseRegister()
407 if (RegNo == 0) in ParseRegister()
408 RegNo = MatchRegisterName(LowercaseString(Tok.getString())); in ParseRegister()
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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp72 unsigned RegNo,
77 unsigned RegNo,
82 unsigned RegNo,
87 unsigned RegNo,
92 unsigned RegNo,
97 unsigned RegNo,
107 unsigned RegNo,
112 unsigned RegNo,
117 unsigned RegNo,
122 unsigned RegNo,
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/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
77 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
593 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) in ParseRegister() argument
598 RegNo = 0; in ParseRegister()
603 if (matchRegisterName(Tok, RegNo, regKind)) { in ParseRegister()
781 unsigned RegNo, RegKind; in parseOperand() local
782 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) in parseOperand()
787 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
840 unsigned RegNo; in parseSparcAsmOperand() local
842 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { in parseSparcAsmOperand()
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h725 inline bool isX86_64ExtendedReg(unsigned RegNo) { in isX86_64ExtendedReg() argument
726 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM15) || in isX86_64ExtendedReg()
727 (RegNo >= X86::XMM24 && RegNo <= X86::XMM31) || in isX86_64ExtendedReg()
728 (RegNo >= X86::YMM8 && RegNo <= X86::YMM15) || in isX86_64ExtendedReg()
729 (RegNo >= X86::YMM24 && RegNo <= X86::YMM31) || in isX86_64ExtendedReg()
730 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM15) || in isX86_64ExtendedReg()
731 (RegNo >= X86::ZMM24 && RegNo <= X86::ZMM31)) in isX86_64ExtendedReg()
734 switch (RegNo) { in isX86_64ExtendedReg()
753 static inline bool is32ExtendedReg(unsigned RegNo) { in is32ExtendedReg() argument
754 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || in is32ExtendedReg()
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/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp153 unsigned RegNo, in DecodeIntRegsRegisterClass() argument
156 if (RegNo > 31) in DecodeIntRegsRegisterClass()
158 unsigned Reg = IntRegDecoderTable[RegNo]; in DecodeIntRegsRegisterClass()
164 unsigned RegNo, in DecodeI64RegsRegisterClass() argument
167 if (RegNo > 31) in DecodeI64RegsRegisterClass()
169 unsigned Reg = IntRegDecoderTable[RegNo]; in DecodeI64RegsRegisterClass()
176 unsigned RegNo, in DecodeFPRegsRegisterClass() argument
179 if (RegNo > 31) in DecodeFPRegsRegisterClass()
181 unsigned Reg = FPRegDecoderTable[RegNo]; in DecodeFPRegsRegisterClass()
188 unsigned RegNo, in DecodeDFPRegsRegisterClass() argument
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/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp208 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass() argument
210 assert(RegNo < N && "Invalid register number"); in decodeRegisterClass()
211 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
215 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRRCRegisterClass() argument
218 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRCRegisterClass()
221 static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRRC0RegisterClass() argument
224 return decodeRegisterClass(Inst, RegNo, CRRegs); in DecodeCRRC0RegisterClass()
227 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRBITRCRegisterClass() argument
230 return decodeRegisterClass(Inst, RegNo, CRBITRegs); in DecodeCRBITRCRegisterClass()
233 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeF4RCRegisterClass() argument
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/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp34 unsigned RegNo, uint64_t Address,
37 unsigned RegNo,
40 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
46 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
49 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
56 unsigned RegNo, uint64_t Address,
58 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
62 unsigned RegNo, uint64_t Address,
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp30 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { in printRegName()
31 OS << getRegisterName(RegNo); in printRegName()
176 unsigned RegNo; in printcrbitm() local
179 case PPC::CR0: RegNo = 0; break; in printcrbitm()
180 case PPC::CR1: RegNo = 1; break; in printcrbitm()
181 case PPC::CR2: RegNo = 2; break; in printcrbitm()
182 case PPC::CR3: RegNo = 3; break; in printcrbitm()
183 case PPC::CR4: RegNo = 4; break; in printcrbitm()
184 case PPC::CR5: RegNo = 5; break; in printcrbitm()
185 case PPC::CR6: RegNo = 6; break; in printcrbitm()
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/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp39 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { in printRegName()
40 const char *RegName = getRegisterName(RegNo); in printRegName()
358 unsigned RegNo; in printcrbitm() local
361 case PPC::CR0: RegNo = 0; break; in printcrbitm()
362 case PPC::CR1: RegNo = 1; break; in printcrbitm()
363 case PPC::CR2: RegNo = 2; break; in printcrbitm()
364 case PPC::CR3: RegNo = 3; break; in printcrbitm()
365 case PPC::CR4: RegNo = 4; break; in printcrbitm()
366 case PPC::CR5: RegNo = 5; break; in printcrbitm()
367 case PPC::CR6: RegNo = 6; break; in printcrbitm()
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/external/llvm/include/llvm/MC/
DMCRegisterInfo.h328 const MCRegisterDesc &operator[](unsigned RegNo) const {
329 assert(RegNo < NumRegs &&
331 return Desc[RegNo];
336 const MCRegisterDesc &get(unsigned RegNo) const { in get() argument
337 return operator[](RegNo); in get()
353 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
367 const char *getName(unsigned RegNo) const { in getName() argument
368 return RegStrings + get(RegNo).Name; in getName()
427 uint16_t getEncodingValue(unsigned RegNo) const { in getEncodingValue() argument
428 assert(RegNo < NumRegs && in getEncodingValue()
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/external/llvm/lib/CodeGen/AsmPrinter/
DDbgValueHistoryCalculator.cpp81 static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, in dropRegDescribedVar() argument
83 const auto &I = RegVars.find(RegNo); in dropRegDescribedVar()
84 assert(RegNo != 0U && I != RegVars.end()); in dropRegDescribedVar()
95 static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, in addRegDescribedVar() argument
97 assert(RegNo != 0U); in addRegDescribedVar()
98 auto &VarSet = RegVars[RegNo]; in addRegDescribedVar()
118 static void clobberRegisterUses(RegDescribedVarsMap &RegVars, unsigned RegNo, in clobberRegisterUses() argument
121 const auto &I = RegVars.find(RegNo); in clobberRegisterUses()
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp66 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
69 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
72 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
75 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
78 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
81 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
84 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
87 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
90 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
93 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyAsmPrinter.cpp84 MVT getRegType(unsigned RegNo) const;
96 MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const { in getRegType()
97 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType()
101 DEBUG(errs() << "Unknown type for register number: " << RegNo); in getRegType()
111 unsigned RegNo = MO.getReg(); in regToString() local
112 assert(TargetRegisterInfo::isVirtualRegister(RegNo) && in regToString()
114 assert(!MFI->isVRegStackified(RegNo)); in regToString()
115 unsigned WAReg = MFI->getWAReg(RegNo); in regToString()
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp752 bool OmitRegisterFromClobberLists(unsigned RegNo) override;
813 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
815 void SetFrameRegister(unsigned RegNo) override;
869 bool X86AsmParser::ParseRegister(unsigned &RegNo, in ParseRegister() argument
872 RegNo = 0; in ParseRegister()
890 RegNo = MatchRegisterName(Tok.getString()); in ParseRegister()
893 if (RegNo == 0) in ParseRegister()
894 RegNo = MatchRegisterName(Tok.getString().lower()); in ParseRegister()
898 if (isParsingInlineAsm() && isParsingIntelSyntax() && RegNo == X86::EFLAGS) in ParseRegister()
899 RegNo = 0; in ParseRegister()
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DX86Operand.h45 unsigned RegNo; member
99 return Reg.RegNo; in getReg()
390 static unsigned getGR32FromGR64(unsigned RegNo) { in getGR32FromGR64()
391 switch (RegNo) { in getGR32FromGR64()
415 unsigned RegNo = getReg(); in addGR32orGR64Operands() local
416 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo)) in addGR32orGR64Operands()
417 RegNo = getGR32FromGR64(RegNo); in addGR32orGR64Operands()
418 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
476 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
480 Res->Reg.RegNo = RegNo;
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.h29 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
40 virtual StringRef getRegName(unsigned RegNo) const { in getRegName() argument
41 return getRegisterName(RegNo); in getRegName()
43 static const char *getRegisterName(unsigned RegNo,
180 StringRef getRegName(unsigned RegNo) const override { in getRegName() argument
181 return getRegisterName(RegNo); in getRegName()
183 static const char *getRegisterName(unsigned RegNo,
/external/llvm/lib/Target/Mips/
DMipsTargetStreamer.h44 virtual void emitDirectiveSetAtWithArg(unsigned RegNo);
85 virtual void emitDirectiveCpLoad(unsigned RegNo);
89 virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
208 void emitDirectiveSetAtWithArg(unsigned RegNo) override;
249 void emitDirectiveCpLoad(unsigned RegNo) override;
260 void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
313 void emitDirectiveCpLoad(unsigned RegNo) override;
316 void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/
DMBlazeAsmParser.cpp40 MBlazeOperand *ParseRegister(unsigned &RegNo);
45 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
388 bool MBlazeAsmParser::ParseRegister(unsigned &RegNo, in ParseRegister() argument
390 return (ParseRegister(RegNo) == 0); in ParseRegister()
393 MBlazeOperand *MBlazeAsmParser::ParseRegister(unsigned &RegNo) { in ParseRegister() argument
400 RegNo = MatchRegisterName(getLexer().getTok().getIdentifier()); in ParseRegister()
401 if (RegNo == 0) in ParseRegister()
405 return MBlazeOperand::CreateReg(RegNo, S, E); in ParseRegister()
461 unsigned RegNo; in ParseOperand() local
462 Op = ParseRegister(RegNo); in ParseOperand()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FloatingPoint.cpp188 unsigned getSlot(unsigned RegNo) const { in getSlot()
189 assert(RegNo < NumFPRegs && "Regno out of range!"); in getSlot()
190 return RegMap[RegNo]; in getSlot()
194 bool isLive(unsigned RegNo) const { in isLive()
195 unsigned Slot = getSlot(RegNo); in isLive()
196 return Slot < StackTop && Stack[Slot] == RegNo; in isLive()
208 bool isScratchReg(unsigned RegNo) { in isScratchReg()
209 return RegNo > 8 && RegNo < NumFPRegs; in isScratchReg()
221 unsigned getSTReg(unsigned RegNo) const { in getSTReg()
222 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; in getSTReg()
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/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h312 unsigned getCostPerUse(unsigned RegNo) const { in getCostPerUse() argument
313 return InfoDesc[RegNo].CostPerUse; in getCostPerUse()
318 bool isInAllocatableClass(unsigned RegNo) const { in isInAllocatableClass() argument
319 return InfoDesc[RegNo].inAllocatableClass; in isInAllocatableClass()
373 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
378 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;

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