| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 756 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias() argument
757 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) in isAnyMOVZMovAlias()
764 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias() argument
765 if (RegWidth == 32) in isMOVZMovAlias()
775 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias() argument
777 if (isAnyMOVZMovAlias(Value, RegWidth)) in isMOVNMovAlias()
781 if (RegWidth == 32) in isMOVNMovAlias()
784 return isMOVZMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
787 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias() argument
788 if (isAnyMOVZMovAlias(Value, RegWidth)) in isAnyMOVWMovAlias()
[all …]
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 586 …bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1,…
587 …ol ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, unsigned& RegWidth);
741 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass() argument
743 switch (RegWidth) { in getRegClass()
753 switch (RegWidth) { in getRegClass()
760 switch (RegWidth) { in getRegClass()
804 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind… in AddNextRegisterToList() argument
808 …if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { Reg = AMDGPU::EXEC; RegWidth = 2; return … in AddNextRegisterToList()
809 …::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { Reg = AMDGPU::FLAT_SCR; RegWidth = 2; return true;… in AddNextRegisterToList()
810 …if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { Reg = AMDGPU::VCC; RegWidth = 2; return tru… in AddNextRegisterToList()
[all …]
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 229 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
236 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
243 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
246 if (RegWidth == 32) in printInst()
249 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { in printInst()
251 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
260 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
262 MI->getOperand(2).getImm(), RegWidth); in printInst()
263 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) { in printInst()
265 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 863 template<int RegWidth, int Shift>
871 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth); in isMOVZMovAlias()
874 template<int RegWidth, int Shift>
882 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
3793 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
3796 RegWidth = 64; in MatchAndEmitInstruction()
3798 RegWidth = 32; in MatchAndEmitInstruction()
3800 if (LSB >= RegWidth) in MatchAndEmitInstruction()
3803 if (Width < 1 || Width > RegWidth) in MatchAndEmitInstruction()
3808 if (RegWidth == 32) in MatchAndEmitInstruction()
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetLowering.h | 580 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local
581 return (BitWidth + RegWidth - 1) / RegWidth; in getNumRegisters()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 876 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local
877 return (BitWidth + RegWidth - 1) / RegWidth; in getNumRegisters()
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| /external/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 4780 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst() local
4782 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth()) in optimizeSwitchInst()
4791 auto *NewType = Type::getIntNTy(Context, RegWidth); in optimizeSwitchInst()
4808 NarrowConst.zext(RegWidth) : NarrowConst.sext(RegWidth); in optimizeSwitchInst()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 196 template<unsigned RegWidth>
198 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosOperand()
2348 unsigned RegWidth) { in SelectCVTFixedPosOperand() argument
2384 if (FBits == 0 || FBits > RegWidth) return false; in SelectCVTFixedPosOperand()
|