Home
last modified time | relevance | path

Searched refs:SALU (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td22 field bits<1> SALU = 0;
58 let TSFlags{3} = SALU;
288 let SALU = 1;
299 let SALU = 1;
311 let SALU = 1;
325 let SALU = 1;
337 let SALU = 1;
DSIInstrInfo.h184 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
188 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
360 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
DSIDefines.h19 SALU = 1 << 3, enumerator
DSISchedule.td45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
DSIInstructions.td1923 let usesCustomInserter = 1, SALU = 1 in {
1926 } // End let usesCustomInserter = 1, SALU = 1
1940 let SALU = 1;
2009 let SALU = 1;
2020 let SALU = 1;
2030 let SALU = 1;
2122 let SALU = 1;
/external/llvm/test/CodeGen/AMDGPU/
Dsgpr-control-flow.ll4 ; Most SALU instructions ignore control flow, so we need to make sure
Dsplit-scalar-i64-add.ll6 ; SALU, but the upper half does not. The addc expects the carry bit
Duniform-cfg.ll121 ; be selected for the SALU and then later moved to the VALU.
146 ; be selected for the SALU and then later moved to the VALU.
Dxor.ll152 ; use an SALU instruction for this.
Dctpop.ll271 ; FIXME: We currently disallow SALU instructions in all branches,
Dand.ll59 ; FIXME: We should really duplicate the constant so that the SALU use
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td26 // Special bitcast node for sharing VCC register between VALU and SALU