| /external/llvm/test/CodeGen/AMDGPU/ |
| D | use-sgpr-multiple-times.ll | 11 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
12 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
21 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
22 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
99 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
100 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
109 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
110 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]]
120 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
121 ; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
[all …]
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| D | sgpr-control-flow.ll | 7 ; If the branch decision is made based on a value in an SGPR then all
38 ; SI: s_add_i32 [[SGPR:s[0-9]+]]
39 ; SI-NOT: s_add_i32 [[SGPR]]
62 ; FIXME: Should write to different SGPR pairs instead of copying to
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| D | add_i64.ll | 20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
32 ; SGPR as other operand.
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| D | spill-alloc-sgpr-init-bug.ll | 3 ; On Tonga and Iceland, limited SGPR availability means care must be taken to
17 ; mark 128-bit SGPR registers as used so they are unavailable for the
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| D | v_cndmask.ll | 22 ; This requires slightly trickier SGPR operand legalization since the
23 ; single constant bus SGPR usage is the last operand, and it should
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| D | sgpr-copy-duplicate-operand.ll | 4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
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| D | move-addr64-rsrc-dead-subreg-writes.ll | 6 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
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| D | sint_to_fp.f64.ll | 14 ; uses an SGPR (implicit vcc).
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| D | spill-scavenge-offset.ll | 8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
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| D | uint_to_fp.f64.ll | 74 ; uses an SGPR (implicit vcc).
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| D | si-lod-bias.ll | 4 ; This shader has the potential to generated illegal VGPR to SGPR copies if
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| D | madak.ll | 102 ; We can't use an SGPR when forming madak
195 ; SIFoldOperands should not fold the SGPR copy into the instruction
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| D | salu-to-valu.ll | 169 ; Original scalar load uses SGPR offset on SI and 32-bit literal on
437 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
438 ; GCN: v_cmp_le_u32_e32 vcc, [[SGPR]], v{{[0-9]+}}
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| D | add.ll | 140 ; use VCC. The test is designed so that %a will be stored in an SGPR and
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| D | select-vectors.ll | 33 ; vector select with SGPR inputs.
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| D | and.ll | 61 ; directly without copying from the SGPR.
79 ; Second use is another SGPR use of the constant.
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| D | commute_modifiers.ll | 50 ; FIXME: Should use SGPR for literal.
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| D | fmin_legacy.ll | 10 ; super register, so we can't fold both SGPR operands even though they
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 102 // SGPR registers
104 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
125 // SGPR 32-bit registers
127 (add (sequence "SGPR%u", 0, 103))> {
131 // SGPR 64-bit registers
136 // SGPR 128-bit registers
143 // SGPR 256-bit registers
154 // SGPR 512-bit registers
358 // SSrc_* Operands with an SGPR or a 32-bit immediate
370 // SCSrc_* Operands with an SGPR or a inline constant
[all …]
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| D | SIIntrinsics.td | 24 [llvm_anyint_ty, // rsrc(SGPR)
28 llvm_i32_ty, // soffset(SGPR)
42 [llvm_anyint_ty, // rsrc(SGPR)
44 llvm_i32_ty, // soffset(SGPR)
59 llvm_v8i32_ty, // rsrc(SGPR)
60 llvm_v4i32_ty, // sampler(SGPR)
75 llvm_v8i32_ty, // rsrc(SGPR)
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| D | AMDGPU.td | 79 "VI SGPR initilization bug requiring a fixed SGPR allocation size"
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| D | SIInstrInfo.cpp | 2175 unsigned SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in readlaneVGPRToSGPR() local
2177 get(AMDGPU::V_READFIRSTLANE_B32), SGPR) in readlaneVGPRToSGPR()
2179 SRegs.push_back(SGPR); in readlaneVGPRToSGPR()
2201 unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI); in legalizeOperandsSMRD() local
2202 SBase->setReg(SGPR); in legalizeOperandsSMRD()
2329 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI); in legalizeOperands() local
2330 SRsrc->setReg(SGPR); in legalizeOperands()
2335 unsigned SGPR = readlaneVGPRToSGPR(SSamp->getReg(), MI, MRI); in legalizeOperands() local
2336 SSamp->setReg(SGPR); in legalizeOperands()
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 193 llvm_v8i32_ty, // rsrc(SGPR)
208 llvm_v8i32_ty, // rsrc(SGPR)
223 llvm_v8i32_ty, // rsrc(SGPR)
246 llvm_v8i32_ty, // rsrc(SGPR)
254 [llvm_v4i32_ty, // rsrc(SGPR)
256 llvm_i32_ty, // offset(SGPR/VGPR/imm)
266 llvm_v4i32_ty, // rsrc(SGPR)
268 llvm_i32_ty, // offset(SGPR/VGPR/imm)
278 llvm_v4i32_ty, // rsrc(SGPR)
280 llvm_i32_ty, // offset(SGPR/VGPR/imm)
[all …]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIGenRegisterInfo.pl | 128 my @SGPR;
131 $SGPR[$i] = "SGPR$i";
205 for (my $i = 0; $i <= $#SGPR; $i++) {
206 push (@{$hw_values{$i}}, $SGPR[$i]);
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| /external/clang/test/SemaOpenCL/ |
| D | amdgpu-num-register-attrs.cl | 23 // Check 0 SGPR is accepted.
26 // Check both 0 SGPR and VGPR is accepted.
|