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Searched refs:SIGN_EXTEND (Results 1 – 25 of 73) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
568 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, in getCastInstrCost()
571 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, in getCastInstrCost()
572 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, in getCastInstrCost()
617 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
619 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, in getCastInstrCost()
621 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
623 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
625 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, in getCastInstrCost()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
205 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
207 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
209 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
211 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp105 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
107 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
113 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
115 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
117 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
119 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
121 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
250 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 }, in getCastInstrCost()
/external/llvm/test/CodeGen/AArch64/
Darm64-AnInfiniteLoopInDAGCombine.ll10 ; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp323 setOperationAction(ISD::SIGN_EXTEND, MVT::i128, Custom); in SPUTargetLowering()
452 setTargetDAGCombine(ISD::SIGN_EXTEND); in SPUTargetLowering()
727 result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result); in LowerLOAD()
2208 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2209 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); in LowerI8Math()
2219 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2220 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); in LowerI8Math()
2269 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2271 unsigned N1Opc = ISD::SIGN_EXTEND; in LowerI8Math()
2284 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h359 SIGN_EXTEND, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h392 SIGN_EXTEND, enumerator
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp713 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1079 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); in visit()
1152 case ISD::SIGN_EXTEND: in combine()
1470 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADD()
1472 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
2002 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
2003 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
2120 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); in visitSMUL_LOHI()
2121 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); in visitSMUL_LOHI()
2220 N0.getOpcode() == ISD::SIGN_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
[all …]
DFastISel.cpp274 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, in getRegForGEPIndex()
629 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); in SelectCall()
963 return SelectCast(I, ISD::SIGN_EXTEND); in SelectOperator()
DLegalizeVectorOps.cpp169 case ISD::SIGN_EXTEND: in LegalizeOp()
DLegalizeFloatTypes.cpp560 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in SoftenFloatRes_XINT_TO_FP()
1180 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP()
1187 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP()
1191 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src); in ExpandFloatRes_XINT_TO_FP()
DLegalizeVectorTypes.cpp89 case ISD::SIGN_EXTEND: in ScalarizeVectorResult()
466 case ISD::SIGN_EXTEND: in SplitVectorResult()
991 case ISD::SIGN_EXTEND: in SplitVectorOperand()
1287 case ISD::SIGN_EXTEND: in WidenVectorResult()
2042 case ISD::SIGN_EXTEND: in WidenVectorOperand()
DLegalizeIntegerTypes.cpp92 case ISD::SIGN_EXTEND: in PromoteIntegerResult()
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
396 if (N->getOpcode() == ISD::SIGN_EXTEND) in PromoteIntRes_INT_EXTEND()
775 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; in PromoteIntegerOperand()
1109 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult()
2136 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); in ExpandIntRes_SIGN_EXTEND()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp260 Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
317 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp983 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1395 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); in visit()
1484 case ISD::SIGN_EXTEND: in combine()
1758 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADD()
1760 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
2495 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
2496 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
2609 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); in visitSMUL_LOHI()
2610 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); in visitSMUL_LOHI()
2722 N0.getOpcode() == ISD::SIGN_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
[all …]
DLegalizeVectorOps.cpp298 case ISD::SIGN_EXTEND: in LegalizeOp()
453 ISD::SIGN_EXTEND; in PromoteINT_TO_FP()
DLegalizeVectorTypes.cpp96 case ISD::SIGN_EXTEND: in ScalarizeVectorResult()
438 case ISD::SIGN_EXTEND: in ScalarizeVectorOperand()
662 case ISD::SIGN_EXTEND: in SplitVectorResult()
1502 case ISD::SIGN_EXTEND: in SplitVectorOperand()
2140 case ISD::SIGN_EXTEND: in WidenVectorResult()
2459 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val); in WidenVecRes_EXTEND_VECTOR_INREG()
3091 case ISD::SIGN_EXTEND: in WidenVectorOperand()
3178 case ISD::SIGN_EXTEND: in WidenVecOp_EXTEND()
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430ISelLowering.cpp121 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); in MSP430TargetLowering()
191 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation()
479 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering()
198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering()
DSIISelLowering.cpp424 && Arg0.getOpcode() == ISD::SIGN_EXTEND in PerformDAGCombine()
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp416 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
589 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp114 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); in MSP430TargetLowering()
191 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation()
591 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp661 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul()
690 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul()
1458 case ISD::SIGN_EXTEND: in isValueExtension()
DHexagonISelLowering.cpp749 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1266 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND in LowerSETCC()
1286 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS); in LowerSETCC()
1287 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS); in LowerSETCC()
1292 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS); in LowerSETCC()
1293 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS); in LowerSETCC()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.h242 return ISD::SIGN_EXTEND; in getExtendForAtomicOps()

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