| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstrInfo.cpp | 25 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm) in SIInstrInfo() function in SIInstrInfo
31 const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const in getRegisterInfo()
37 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
52 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, in getMovImmInstr()
63 bool SIInstrInfo::isMov(unsigned Opcode) const in isMov()
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| D | SIInstrInfo.h | 23 class SIInstrInfo : public AMDGPUInstrInfo {
29 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
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| D | Makefile.sources | 20 SIInstrInfo.td \
72 SIInstrInfo.cpp \
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| D | SIISelLowering.h | 24 const SIInstrInfo * TII;
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| D | AMDGPUTargetMachine.cpp | 63 InstrInfo = new SIInstrInfo(*this); in AMDGPUTargetMachine()
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| D | AMDGPUInstructions.td | 163 include "SIInstrInfo.td"
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| /external/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 45 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) in getHazardType()
48 if (SIInstrInfo::isVMEM(*MI) && checkVMEMHazards(MI) > 0) in getHazardType()
51 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0) in getHazardType()
62 if (SIInstrInfo::isSMRD(*MI)) in PreEmitNoops()
65 if (SIInstrInfo::isVMEM(*MI)) in PreEmitNoops()
68 if (SIInstrInfo::isDPP(*MI)) in PreEmitNoops()
85 const SIInstrInfo *TII = ST.getInstrInfo(); in AdvanceCycle()
164 if (!MI || !SIInstrInfo::isSMRD(*MI)) in checkSMEMSoftClauseHazards()
199 const SIInstrInfo *TII = ST.getInstrInfo(); in checkSMRDHazards()
224 const SIInstrInfo *TII = ST.getInstrInfo(); in checkVMEMHazards()
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| D | SIInstrInfo.cpp | 31 SIInstrInfo::SIInstrInfo(const SISubtarget &ST) in SIInstrInfo() function in SIInstrInfo
78 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
93 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr()
205 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, in getMemOpBaseRegImmOfs()
299 bool SIInstrInfo::shouldClusterMemOps(MachineInstr &FirstLdSt, in shouldClusterMemOps()
341 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
502 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const { in commuteOpcode()
522 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { in getMovOpcode()
570 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, in storeRegToStackSlot()
669 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, in loadRegFromStackSlot()
[all …]
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| D | SIShrinkInstructions.cpp | 80 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, in canShrink()
129 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates()
193 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKImmOperand()
203 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIFoldOperands.cpp | 134 const SIInstrInfo *TII) { in tryAddToFoldList()
195 const SIInstrInfo *TII, const SIRegisterInfo &TRI, in foldOperand()
302 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SISchedule.td | 15 const SIInstrInfo *TII =
16 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
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| D | AMDGPUSubtarget.h | 342 SIInstrInfo InstrInfo;
351 const SIInstrInfo *getInstrInfo() const override { in getInstrInfo()
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| D | SIRegisterInfo.cpp | 255 if (!SIInstrInfo::isMUBUF(*MI)) in getFrameIndexInstrOffset()
283 const SIInstrInfo *TII = Subtarget.getInstrInfo(); in materializeFrameBaseRegister()
309 const SIInstrInfo *TII = Subtarget.getInstrInfo(); in resolveFrameIndex()
364 return SIInstrInfo::isMUBUF(*MI) && isUInt<12>(Offset); in isFrameOffsetLegal()
423 const SIInstrInfo *TII = ST.getInstrInfo(); in buildScratchLoadStore()
504 const SIInstrInfo *TII = ST.getInstrInfo(); in eliminateFrameIndex()
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| D | GCNHazardRecognizer.h | 26 class SIInstrInfo; variable
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| D | SIDebuggerInsertNops.cpp | 74 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIFixSGPRCopies.cpp | 178 const SIInstrInfo *TII, in foldVGPRCopyIntoRegSequence()
243 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIFrameLowering.cpp | 63 const SIInstrInfo *TII = ST.getInstrInfo(); in emitPrologue()
303 const SIInstrInfo *TII = ST.getInstrInfo(); in emitDebuggerPrologue()
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| D | CMakeLists.txt | 71 SIInstrInfo.cpp
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| D | SILowerI1Copies.cpp | 70 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | AMDGPUMCInstLower.cpp | 45 case SIInstrInfo::MO_GOTPCREL: return MCSymbolRefExpr::VK_GOTPCREL; in getVariantKind()
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| D | SIInstrInfo.h | 25 class SIInstrInfo final : public AMDGPUInstrInfo {
100 explicit SIInstrInfo(const SISubtarget &);
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| D | SIISelLowering.cpp | 534 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); in shouldConvertConstantLoadToIntImm()
1079 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); in splitKillBlock()
1135 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); in EmitInstrWithCustomInserter()
1145 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); in EmitInstrWithCustomInserter()
1537 unsigned GAFlags = SIInstrInfo::MO_NONE) { in buildPCRelGlobalAddress()
1577 SIInstrInfo::MO_GOTPCREL); in LowerGlobalAddress()
3069 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); in analyzeImmediate()
3217 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); in PostISelFolding()
3236 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); in AdjustInstrPostInstrSelection()
3313 const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); in wrapAddr64Rsrc()
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| D | SIMachineScheduler.h | 422 const SIInstrInfo *SITII;
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | schedule-global-loads.ll | 23 ; Test for a crach in SIInstrInfo::areLoadsFromSameBasePtr() when checking
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| D | schedule-kernel-arg-loads.ll | 21 ; Test for a crash in SIInstrInfo::areLoadsFromSameBasePtr() when
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