Searched refs:SOPP (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 75 SOPP Instructions
78 Unless otherwise mentioned, all SOPP instructions that have one or more
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstructions.td | 601 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
609 def S_BRANCH : SOPP <
615 def S_CBRANCH_SCC0 : SOPP <
619 def S_CBRANCH_SCC1 : SOPP <
626 def S_CBRANCH_VCCZ : SOPP <
631 def S_CBRANCH_VCCNZ : SOPP <
638 def S_CBRANCH_EXECZ : SOPP <
643 def S_CBRANCH_EXECNZ : SOPP <
655 def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16",
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| D | SIInstrInfo.td | 335 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
346 let EncodingType = 10; // SIInstrEncodingType::SOPP
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 29 field bits<1> SOPP = 0;
65 let TSFlags{9} = SOPP;
331 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
338 let SOPP = 1;
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| D | SIInstructions.td | 421 // SOPP Instructions
424 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
428 def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
437 def S_BRANCH : SOPP <
444 def S_CBRANCH_SCC0 : SOPP <
448 def S_CBRANCH_SCC1 : SOPP <
456 def S_CBRANCH_VCCZ : SOPP <
460 def S_CBRANCH_VCCNZ : SOPP <
467 def S_CBRANCH_EXECZ : SOPP <
471 def S_CBRANCH_EXECNZ : SOPP <
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| D | SIDefines.h | 26 SOPP = 1 << 9, enumerator
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| D | SIInstrInfo.h | 240 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
244 return get(Opcode).TSFlags & SIInstrFlags::SOPP; in isSOPP()
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 47 SOPP = 10, enumerator
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