Searched refs:SRLG (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-06.ll | 5 ; Check the low end of the SRLG range.
14 ; Check the high end of the defined SRLG range.
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| D | shift-12.ll | 76 ; Test removal of AND mask from SRLG.
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| D | insert-05.ll | 83 ; Check that SRLG is still used if some of the high bits are known to be 0
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| /external/v8/src/s390/ |
| D | disasm-s390.cc | 1127 case SRLG: in DecodeSixByte()
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| D | constants-s390.h | 807 SRLG = 0xEB0C, // Shift Right Single Logical (64) enumerator
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| D | simulator-s390.h | 1133 EVALUATE(SRLG);
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| D | assembler-s390.cc | 2452 rsy_form(SRLG, r1, r3, opnd, 0); in srlg()
2457 rsy_form(SRLG, r1, r3, r0, opnd.immediate()); in srlg()
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| D | simulator-s390.cc | 1354 EvalTable[SRLG] = &Simulator::Evaluate_SRLG; in EvalTableInit()
4668 case SRLG: { in DecodeSixByte()
5034 case SRLG: { in DecodeSixByteBitShift()
5052 } else if (op == SRLG) { in DecodeSixByteBitShift()
11696 EVALUATE(SRLG) { in EVALUATE() argument
11697 DCHECK_OPCODE(SRLG); in EVALUATE()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1218 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
1741 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
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