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Searched refs:SSE3 (Results 1 – 25 of 61) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dhaddsub-2.ll2 …%s -mtriple=x86_64-unknown -mattr=+sse2,+sse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSE3
124 ; SSE3-LABEL: phadd_d_test1:
125 ; SSE3: # BB#0:
126 ; SSE3-NEXT: movd %xmm0, %eax
127 ; SSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,2,3]
128 ; SSE3-NEXT: movd %xmm2, %ecx
129 ; SSE3-NEXT: addl %eax, %ecx
130 ; SSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
131 ; SSE3-NEXT: movd %xmm2, %eax
132 ; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
[all …]
Dhaddsub.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
6 ; SSE3-LABEL: haddpd1:
7 ; SSE3: # BB#0:
8 ; SSE3-NEXT: haddpd %xmm1, %xmm0
9 ; SSE3-NEXT: retq
22 ; SSE3-LABEL: haddpd2:
23 ; SSE3: # BB#0:
24 ; SSE3-NEXT: haddpd %xmm1, %xmm0
25 ; SSE3-NEXT: retq
38 ; SSE3-LABEL: haddpd3:
[all …]
Dvector-lzcnt-128.ll3 …known-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
33 ; SSE3-LABEL: testv2i64:
34 ; SSE3: # BB#0:
35 ; SSE3-NEXT: movd %xmm0, %rax
36 ; SSE3-NEXT: bsrq %rax, %rax
37 ; SSE3-NEXT: movl $127, %ecx
38 ; SSE3-NEXT: cmoveq %rcx, %rax
39 ; SSE3-NEXT: xorq $63, %rax
40 ; SSE3-NEXT: movd %rax, %xmm1
41 ; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
[all …]
Dpromote-vec3.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
9 ; SSE3-LABEL: zext_i8:
10 ; SSE3: # BB#0:
11 ; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %eax
12 ; SSE3-NEXT: pxor %xmm0, %xmm0
13 ; SSE3-NEXT: pxor %xmm1, %xmm1
14 ; SSE3-NEXT: pinsrw $0, %eax, %xmm1
15 ; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %eax
16 ; SSE3-NEXT: pinsrw $1, %eax, %xmm1
17 ; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %eax
[all …]
Dvector-popcnt-128.ll3 …known-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
31 ; SSE3-LABEL: testv2i64:
32 ; SSE3: # BB#0:
33 ; SSE3-NEXT: movdqa %xmm0, %xmm1
34 ; SSE3-NEXT: psrlq $1, %xmm1
35 ; SSE3-NEXT: pand {{.*}}(%rip), %xmm1
36 ; SSE3-NEXT: psubq %xmm1, %xmm0
37 ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [3689348814741910323,3689348814741910323]
38 ; SSE3-NEXT: movdqa %xmm0, %xmm2
39 ; SSE3-NEXT: pand %xmm1, %xmm2
[all …]
Dinsertelement-zero.ll3 … -mcpu=x86-64 -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
19 ; SSE3-LABEL: insert_v2f64_z1:
20 ; SSE3: # BB#0:
21 ; SSE3-NEXT: xorpd %xmm1, %xmm1
22 ; SSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
23 ; SSE3-NEXT: retq
54 ; SSE3-LABEL: insert_v4f64_0zz3:
55 ; SSE3: # BB#0:
56 ; SSE3-NEXT: xorpd %xmm2, %xmm2
57 ; SSE3-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
[all …]
Dvector-shuffle-128-v4.ll3 … -mcpu=x86-64 -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
254 ; SSE3-LABEL: shuffle_v4f32_0022:
255 ; SSE3: # BB#0:
256 ; SSE3-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
257 ; SSE3-NEXT: retq
282 ; SSE3-LABEL: shuffle_v4f32_1133:
283 ; SSE3: # BB#0:
284 ; SSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
285 ; SSE3-NEXT: retq
341 ; SSE3-LABEL: shuffle_v4i32_0124:
[all …]
Dvector-tzcnt-128.ll3 …known-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
31 ; SSE3-LABEL: testv2i64:
32 ; SSE3: # BB#0:
33 ; SSE3-NEXT: movd %xmm0, %rax
34 ; SSE3-NEXT: bsfq %rax, %rax
35 ; SSE3-NEXT: movl $64, %ecx
36 ; SSE3-NEXT: cmoveq %rcx, %rax
37 ; SSE3-NEXT: movd %rax, %xmm1
38 ; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
39 ; SSE3-NEXT: movd %xmm0, %rax
[all …]
Dvector-shuffle-128-v2.ll3 … -mcpu=x86-64 -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
118 ; SSE3-LABEL: shuffle_v2f64_00:
119 ; SSE3: # BB#0:
120 ; SSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
121 ; SSE3-NEXT: retq
174 ; SSE3-LABEL: shuffle_v2f64_22:
175 ; SSE3: # BB#0:
176 ; SSE3-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
177 ; SSE3-NEXT: retq
232 ; SSE3-LABEL: shuffle_v2f64_03:
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dhaddsub.ll1 ; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
4 ; SSE3: haddpd1:
5 ; SSE3-NOT: vhaddpd
6 ; SSE3: haddpd
16 ; SSE3: haddpd2:
17 ; SSE3-NOT: vhaddpd
18 ; SSE3: haddpd
28 ; SSE3: haddpd3:
29 ; SSE3-NOT: vhaddpd
30 ; SSE3: haddpd
[all …]
/external/llvm/test/Analysis/CostModel/X86/
Dcmp.ll2 …macosx10.8.0 -mcpu=yonah | FileCheck --check-prefix=CHECK --check-prefix=SSE --check-prefix=SSE3 %s
16 ;SSE3: cost of 3 {{.*}} fcmp
24 ;SSE3: cost of 7 {{.*}} fcmp
32 ;SSE3: cost of 14 {{.*}} fcmp
40 ;SSE3: cost of 3 {{.*}} fcmp
48 ;SSE3: cost of 6 {{.*}} fcmp
67 ;SSE3: cost of 1 {{.*}} icmp
75 ;SSE3: cost of 1 {{.*}} icmp
83 ;SSE3: cost of 1 {{.*}} icmp
91 ;SSE3: cost of 8 {{.*}} icmp
[all …]
Dreduction.ll2 …eduxcost=true -analyze -mcpu=corei7 -mtriple=x86_64-apple-darwin | FileCheck %s --check-prefix=SSE3
104 ; SSE3: cost of 2 {{.*}} extractelement
118 ; SSE3: cost of 4 {{.*}} extractelement
158 ; SSE3: cost of 2 {{.*}} extractelement
172 ; SSE3: cost of 3 {{.*}} extractelement
201 ; SSE3: cost of 4 {{.*}} extractelement
229 ; SSE3: cost of 2 {{.*}} extractelement
245 ; SSE3: cost of 4 {{.*}} extractelement
291 ; SSE3: cost of 2 {{.*}} extractelement
307 ; SSE3: cost of 3 {{.*}} extractelement
[all …]
/external/skia/src/core/
DSkCpu.h17 SSE3 = 1 << 2, enumerator
68 features |= SSE3; in Supports()
DSkCpu.cpp47 if (abcd[2] & (1<< 0)) { features |= SkCpu:: SSE3; } in read_cpu_features()
/external/swiftshader/src/Common/
DCPUID.hpp54 static bool SSE3; member in sw::CPUID
109 return SSE3 && enableSSE3; in supportsSSE3()
DCPUID.cpp36 bool CPUID::SSE3 = detectSSE3(); member in sw::CPUID
206 return SSE3 = (registers[2] & 0x00000001) != 0; in detectSSE3()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86Subtarget.h45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42 enumerator
175 bool hasSSE3() const { return X86SSELevel >= SSE3; } in hasSSE3()
DX86GenSubtargetInfo.inc78 { "sse3", "Enable SSE3 instructions", X86::FeatureSSE3, X86::FeatureSSE2 },
179 if ((Bits & X86::FeatureSSE3) != 0 && X86SSELevel < SSE3) X86SSELevel = SSE3;
DX86.td50 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
51 "Enable SSE3 instructions",
/external/libchrome/base/
Dcpu.h24 SSE3, enumerator
Dcpu.cc232 if (has_sse3()) return SSE3; in GetIntelMicroArchitecture()
/external/eigen/Eigen/
DCore291 return "AVX512, FMA, AVX2, AVX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2";
293 return "AVX SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2";
295 return "SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2";
297 return "SSE, SSE2, SSE3, SSSE3, SSE4.1";
299 return "SSE, SSE2, SSE3, SSSE3";
301 return "SSE, SSE2, SSE3";
/external/llvm/lib/Target/X86/
DX86Subtarget.h49 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
384 bool hasSSE3() const { return X86SSELevel >= SSE3; } in hasSSE3()
/external/fec/
DREADME73 The latest IA-32 SIMD instruction set, SSE3 (also known as "Prescott
76 introduced with SSE3, and this library currently makes no use of it.
/external/valgrind/docs/internals/
D3_2_BUGSTATUS.txt6 sse3fix = fixed by the SSE3 commits
194 6655/6657 SSE3 feature tests for regtests
424 SSE3 commits: vx1635,1636, v5997
434 sse3fix vx1646 Vfd 106852 x86->IR: fisttp (SSE3)
441 sse3fix vx1646 Vfd 129358 x86->IR: fisttpl (SSE3)

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