Searched refs:SWC1 (Results 1 – 21 of 21) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 79 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) || in isStoreToStackSlot()
179 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1; in storeRegToStackSlot()
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| D | MipsInstrFPU.td | 202 def SWC1 : FPStore<0x39, "swc1", store, FGR32, mem>;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 230 case Mips::SWC1: in isBasePlusOffsetMemoryAccess()
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| /external/valgrind/none/tests/mips32/ |
| D | vfp.stdout.exp-mips32-BE | 72 SWC1
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| D | vfp.stdout.exp-mips32-LE | 72 SWC1
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| D | vfp.stdout.exp-mips32r2-BE | 153 SWC1
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| D | vfp.stdout.exp-mips32r2-LE | 153 SWC1
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| /external/v8/src/mips/ |
| D | constants-mips.h | 392 SWC1 = ((7U << 3) + 1) << kOpcodeShift, enumerator
919 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) |
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| D | assembler-mips.cc | 2252 GenInstrImmediate(SWC1, src.rm(), fd, src.offset_); in swc1()
2255 GenInstrImmediate(SWC1, at, fd, off16); in swc1()
2267 GenInstrImmediate(SWC1, src.rm(), fd, in sdc1()
2271 GenInstrImmediate(SWC1, src.rm(), nextfpreg, in sdc1()
2275 GenInstrImmediate(SWC1, at, fd, off16 + Register::kMantissaOffset); in sdc1()
2278 GenInstrImmediate(SWC1, at, nextfpreg, off16 + Register::kExponentOffset); in sdc1()
2285 GenInstrImmediate(SWC1, src.rm(), fd, in sdc1()
2292 GenInstrImmediate(SWC1, at, fd, off16 + Register::kMantissaOffset); in sdc1()
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| D | disasm-mips.cc | 1651 case SWC1: in DecodeTypeImmediate()
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| D | simulator-mips.cc | 4380 case SWC1: in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 373 SWC1 = ((7U << 3) + 1) << kOpcodeShift, enumerator
954 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) |
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| D | disasm-mips64.cc | 1868 case SWC1: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 2572 GenInstrImmediate(SWC1, src.rm(), fd, src.offset_); in swc1()
2575 GenInstrImmediate(SWC1, at, fd, 0); in swc1()
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| D | simulator-mips64.cc | 4697 case SWC1: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
205 Opc = Mips::SWC1; in storeRegToStack()
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| D | MipsInstrFPU.td | 406 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
648 def : StoreRegImmPat<SWC1, f32>;
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| D | MipsFastISel.cpp | 797 Opc = Mips::SWC1; in emitStore()
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| /external/llvm/test/MC/Mips/ |
| D | target-soft-float.s | 326 # FIXME: SWC1 is correctly rejected but the wrong error message is emitted.
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| /external/valgrind/none/tests/mips64/ |
| D | fpu_load_store.stdout.exp-LE | 2438 --- SWC1 ---
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| D | fpu_load_store.stdout.exp-BE | 2438 --- SWC1 ---
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