| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 200 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
202 if (ShiftAmount >= 32) { in emitDSLL()
203 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
207 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| D | MipsMCCodeEmitter.h | 185 template <unsigned ShiftAmount = 0>
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| D | MipsMCCodeEmitter.cpp | 780 template <unsigned ShiftAmount>
790 OffBits >>= ShiftAmount; in getMemEncoding()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 199 unsigned ShiftAmount; member
351 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
704 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
742 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImmNeg()
1271 unsigned ShiftAmt = isShiftedImm() ? ShiftedImm.ShiftAmount : 0; in addAddSubImmNegOperands()
1667 unsigned ShiftAmount, in CreateShiftedImm() argument
1672 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2274 uint64_t ShiftAmount = 0; in tryParseAddSubImm() local
2280 ShiftAmount = 12; in tryParseAddSubImm()
2284 Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, S, E, in tryParseAddSubImm()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 615 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
622 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
626 ShiftAmount -= 1; in LowerShifts()
629 while (ShiftAmount--) in LowerShifts()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 736 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
743 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
747 ShiftAmount -= 1; in LowerShifts()
750 while (ShiftAmount--) in LowerShifts()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 91 unsigned &ShiftAmount);
2451 const MCExpr *ShiftAmount; in parsePKHImm() local
2453 if (getParser().ParseExpression(ShiftAmount)) { in parsePKHImm()
2457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
2529 const MCExpr *ShiftAmount; in parseShifterImm() local
2531 if (getParser().ParseExpression(ShiftAmount)) { in parseShifterImm()
2535 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
2589 const MCExpr *ShiftAmount; in parseRotImm() local
2591 if (getParser().ParseExpression(ShiftAmount)) { in parseRotImm()
2595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 121 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 827 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
829 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
830 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
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| D | LegalizeDAG.cpp | 1467 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN() local
1469 if (ShiftAmount > 0) { in ExpandFCOPYSIGN()
1470 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1472 } else if (ShiftAmount < 0) { in ExpandFCOPYSIGN()
1473 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1479 if (ShiftAmount > 0) { in ExpandFCOPYSIGN()
1480 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, MagVT); in ExpandFCOPYSIGN()
1482 } else if (ShiftAmount < 0) { in ExpandFCOPYSIGN()
1483 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, MagVT); in ExpandFCOPYSIGN()
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| D | TargetLowering.cpp | 3388 SDValue ShiftAmount = in expandUnalignedLoad() local
3391 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in expandUnalignedLoad()
3506 SDValue ShiftAmount = in expandUnalignedStore() local
3510 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in expandUnalignedStore()
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| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2357 unsigned ShiftAmount = CI2->getValue().countLeadingOnes() - 1; in SimplifyICmpInst() local
2358 Lower = CI2->getValue().shl(ShiftAmount); in SimplifyICmpInst()
2362 unsigned ShiftAmount = CI2->getValue().countLeadingZeros() - 1; in SimplifyICmpInst() local
2364 Upper = CI2->getValue().shl(ShiftAmount) + 1; in SimplifyICmpInst()
2373 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2375 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2376 Lower = CI2->getValue().lshr(ShiftAmount); in SimplifyICmpInst()
2387 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2389 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2393 Upper = CI2->getValue().ashr(ShiftAmount) + 1; in SimplifyICmpInst()
[all …]
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCasts.cpp | 457 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
459 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) in foldVecTruncToExtElt()
470 unsigned Elt = ShiftAmount / DestWidth; in foldVecTruncToExtElt()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1988 SDValue &Src, int &ShiftAmount, in isBitfieldPositioningOp() argument
2023 ShiftAmount = countTrailingZeros(NonZeroBits); in isBitfieldPositioningOp()
2024 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount); in isBitfieldPositioningOp()
2031 if (ShlImm - ShiftAmount != 0 && !BiggerPattern) in isBitfieldPositioningOp()
2033 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount); in isBitfieldPositioningOp()
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| D | AArch64ISelLowering.cpp | 7821 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, in findEXTRHalf() argument
7833 ShiftAmount = N->getConstantOperandVal(1); in findEXTRHalf()
8449 int64_t ShiftAmount; in tryCombineShiftImm() local
8459 ShiftAmount = SplatValue.getSExtValue(); in tryCombineShiftImm()
8461 ShiftAmount = CVN->getSExtValue(); in tryCombineShiftImm()
8492 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) { in tryCombineShiftImm()
8495 DAG.getConstant(-ShiftAmount, dl, MVT::i32)); in tryCombineShiftImm()
8496 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) { in tryCombineShiftImm()
8499 DAG.getConstant(ShiftAmount, dl, MVT::i32)); in tryCombineShiftImm()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1064 template <unsigned Bits, unsigned ShiftAmount = 0>
1072 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) in isMemWithSimmOffset()
1076 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); in isMemWithSimmOffset()
2263 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); in loadImmediate() local
2264 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff; in loadImmediate()
2266 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 205 unsigned &ShiftAmount);
4276 const MCExpr *ShiftAmount; in parsePKHImm() local
4279 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parsePKHImm()
4283 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
4359 const MCExpr *ShiftAmount; in parseShifterImm() local
4361 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseShifterImm()
4365 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
4421 const MCExpr *ShiftAmount; in parseRotImm() local
4423 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseRotImm()
4427 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 473 SDValue ShiftAmount = DAG.getConstant(NumBits, in ExpandUnalignedStore() local
476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
621 SDValue ShiftAmount = DAG.getConstant(NumBits, in ExpandUnalignedLoad() local
623 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in ExpandUnalignedLoad()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1356 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32); in LowerLOAD() local
1357 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount); in LowerLOAD()
1378 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount); in LowerLOAD()
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