| /external/llvm/lib/Linker/ |
| D | IRMover.cpp | 1045 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1047 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1048 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1058 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1059 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1066 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1067 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1080 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1086 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1087 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 123 const MachineOperand &SrcOp = MI->getOperand(1); in interpretAsCopy() local
125 { SrcOp.getReg(), SrcOp.getSubReg() }); in interpretAsCopy()
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| D | HexagonFrameLowering.cpp | 2108 MachineOperand &SrcOp = SI->getOperand(2); in optimizeSpillSlots() local
2110 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2111 SrcOp.getSubReg() }; in optimizeSpillSlots()
2112 auto *RC = getRegClass({SrcOp.getReg(), SrcOp.getSubReg()}); in optimizeSpillSlots()
2125 .addOperand(SrcOp); in optimizeSpillSlots()
2132 if (unsigned SR = SrcOp.getSubReg()) in optimizeSpillSlots()
2133 SrcOp.setReg(HRI.getSubReg(FoundR, SR)); in optimizeSpillSlots()
2135 SrcOp.setReg(FoundR); in optimizeSpillSlots()
2136 SrcOp.setSubReg(0); in optimizeSpillSlots()
2138 SrcOp.setIsKill(false); in optimizeSpillSlots()
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| D | HexagonExpandCondsets.cpp | 249 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
611 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor() argument
615 MachineInstr *MI = SrcOp.getParent(); in genCondTfrFor()
625 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); in genCondTfrFor()
630 .addOperand(SrcOp); in genCondTfrFor()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 244 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false); in ParseConstraint() local
245 if (SrcOp > DestOp) { in ParseConstraint()
246 std::swap(SrcOp, DestOp); in ParseConstraint()
250 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp); in ParseConstraint()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1467 const MachineOperand &SrcOp = MI->getOperand(SrcIdx); in EmitInstruction() local
1474 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1489 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1496 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1511 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1518 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 237 std::pair<unsigned,unsigned> SrcOp = in ParseConstraint() local
239 if (SrcOp > DestOp) in ParseConstraint()
243 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp); in ParseConstraint()
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| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| D | InstructionSimplify.cpp | 1613 Value *SrcOp = LI->getOperand(0); in SimplifyICmpInst() local
1614 Type *SrcTy = SrcOp->getType(); in SimplifyICmpInst()
1623 if (Value *V = SimplifyICmpInst(Pred, SrcOp, in SimplifyICmpInst()
1630 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
1643 SrcOp, RI->getOperand(0), TD, DT, in SimplifyICmpInst()
1659 SrcOp, Trunc, TD, DT, MaxRecurse-1)) in SimplifyICmpInst()
1703 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
1718 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, TD, DT, in SimplifyICmpInst()
1752 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp, in SimplifyICmpInst()
1761 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp, in SimplifyICmpInst()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 861 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
863 assert(!SrcOp.isFPImm()); in expandPostRAPseudo()
864 if (SrcOp.isImm()) { in expandPostRAPseudo()
865 APInt Imm(64, SrcOp.getImm()); in expandPostRAPseudo()
873 assert(SrcOp.isReg()); in expandPostRAPseudo()
875 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
878 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
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| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2452 Value *SrcOp = LI->getOperand(0); in SimplifyICmpInst() local
2453 Type *SrcTy = SrcOp->getType(); in SimplifyICmpInst()
2462 if (Value *V = SimplifyICmpInst(Pred, SrcOp, in SimplifyICmpInst()
2469 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
2482 SrcOp, RI->getOperand(0), Q, in SimplifyICmpInst()
2498 SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
2541 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0), in SimplifyICmpInst()
2556 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse-1)) in SimplifyICmpInst()
2588 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SLT, SrcOp, in SimplifyICmpInst()
2597 if (Value *V = SimplifyICmpInst(ICmpInst::ICMP_SGE, SrcOp, in SimplifyICmpInst()
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| /external/llvm/tools/llvm-c-test/ |
| D | echo.cpp | 429 LLVMValueRef SrcOp = LLVMGetOperand(Src, 0); in CloneInstruction() local
430 LLVMBasicBlockRef SrcBB = LLVMValueAsBasicBlock(SrcOp); in CloneInstruction()
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 2628 for (Value *SrcOp : Instr->operands()) { in scalarizeInstruction()
2630 if (SrcOp == OldInduction) { in scalarizeInstruction()
2631 Params.push_back(getVectorValue(SrcOp)); in scalarizeInstruction()
2636 auto *SrcInst = dyn_cast<Instruction>(SrcOp); in scalarizeInstruction()
2647 Scalars.append(UF, SrcOp); in scalarizeInstruction()
6229 for (Value *SrcOp : Instr->operands()) { in scalarizeInstruction()
6231 if (SrcOp == OldInduction) { in scalarizeInstruction()
6232 Params.push_back(getVectorValue(SrcOp)); in scalarizeInstruction()
6237 Instruction *SrcInst = dyn_cast<Instruction>(SrcOp); in scalarizeInstruction()
6248 Scalars.append(UF, SrcOp); in scalarizeInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.h | 791 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
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| D | X86ISelLowering.cpp | 4883 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, in getVShift() argument
4889 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); in getVShift()
4891 DAG.getNode(Opc, dl, ShVT, SrcOp, in getVShift()
4893 TLI.getShiftAmountTy(SrcOp.getValueType())))); in getVShift()
4897 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, in LowerAsSplatVectorLoad() argument
4903 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { in LowerAsSplatVectorLoad()
5887 SDValue SrcOp, SelectionDAG &DAG, in getVZextMovL() argument
5891 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) in getVZextMovL()
5892 LD = dyn_cast<LoadSDNode>(SrcOp); in getVZextMovL()
5898 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && in getVZextMovL()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 133 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
2025 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, in EmitStackConvert() argument
2031 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). in EmitStackConvert()
2039 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); in EmitStackConvert()
2050 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, in EmitStackConvert()
2054 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, in EmitStackConvert()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
1667 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, in EmitStackConvert() argument
1671 SrcOp.getValueType().getTypeForEVT(*DAG.getContext())); in EmitStackConvert()
1679 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); in EmitStackConvert()
1690 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, in EmitStackConvert()
1694 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, in EmitStackConvert()
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| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 1599 const MachineOperand &SrcOp = Copy->getOperand(1); in constrainLocalCopy() local
1600 unsigned SrcReg = SrcOp.getReg(); in constrainLocalCopy()
1601 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) || !SrcOp.readsReg()) in constrainLocalCopy()
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