| /external/valgrind/none/tests/mips64/ |
| D | load_store.c | 15 TEST1("lb", i, reg_val1); in main()
18 TEST1("lb", i, reg_val2); in main()
22 TEST1("lbu", i, reg_val1); in main()
25 TEST1("lbu", i, reg_val2); in main()
29 TEST1("ld", i, reg_val1); in main()
32 TEST1("ld", i, reg_val2); in main()
36 TEST1("ldl", i, reg_val1); in main()
39 TEST1("ldl", i, reg_val2); in main()
43 TEST1("ldr", i, reg_val1); in main()
46 TEST1("ldr", i, reg_val2); in main()
[all …]
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| D | arithmetic_instruction.c | 31 TEST1("add $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
59 TEST1("addu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
81 TEST1("dadd $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
115 TEST1("daddu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
117 TEST1("daddu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
193 TEST1("dsub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
200 TEST1("dsubu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
202 TEST1("dsubu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
240 TEST1("mul $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
261 TEST1("movn $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
[all …]
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| D | load_indexed_instructions.c | 77 #define TEST1(instruction, offset, mem) \ macro
98 TEST1("ldx", i, reg_val); in main()
100 TEST1("lbux", i, reg_val); in main()
102 TEST1("lwx", i, reg_val); in main()
104 TEST1("lhx", i, reg_val); in main()
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| D | logical_instructions.c | 21 TEST1("and $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
23 TEST1("and $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
54 TEST1("nor $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
56 TEST1("nor $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
62 TEST1("or $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
64 TEST1("or $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
82 TEST1("xor $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
84 TEST1("xor $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
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| D | shift_instructions.c | 50 TEST1("drotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
52 TEST1("drotrv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
79 TEST1("dsllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
81 TEST1("dsllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
108 TEST1("dsrav $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
110 TEST1("dsrav $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
137 TEST1("dsrlv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
139 TEST1("dsrlv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], in main()
155 TEST1("rotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
171 TEST1("sllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], in main()
[all …]
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| D | cvm_lx_ins.c | 69 #define TEST1(instruction, offset, mem) \ macro
98 TEST1("lhux", i, reg_val); in main()
103 TEST1("lwux", i, reg_val); in main()
108 TEST1("lbx", i, reg_val); in main()
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| /external/clang/test/CodeGenObjC/ |
| D | arc-precise-lifetime.m | 44 // CHECK: [[T0:%.*]] = call [[TEST1:%.*]]* @test1_helper()
45 // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST1]]* [[T0]] to i8*
47 // CHECK-NEXT: [[T3:%.*]] = bitcast i8* [[T2]] to [[TEST1]]*
48 // CHECK-NEXT: store [[TEST1]]* [[T3]]
51 // CHECK-NEXT: [[T0:%.*]] = load [[TEST1]]*, [[TEST1]]**
52 // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST1]]* [[T0]] to i8*
54 // CHECK-NEXT: [[T3:%.*]] = bitcast i8* [[T2]] to [[TEST1]]*
56 // CHECK-NEXT: [[T5:%.*]] = bitcast [[TEST1]]* [[T3]] to i8*
61 // CHECK-NEXT: [[T0:%.*]] = load [[TEST1]]*, [[TEST1]]**
62 // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST1]]* [[T0]] to i8*
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | eh-directive-section-multiple-func.s | 13 @ In this example, func1 and func2 should be defined in .TEST1 section.
14 @ It is incorrect if the func2 is in .text, .ARM.extab.TEST1, or
15 @ .ARM.exidx.TEST1 sections.
19 .section .TEST1
54 @ Check the .TEST1 section. There should be two "bx lr" instructions.
58 @ CHECK-NEXT: Name: .TEST1
67 @ Check the .ARM.extab.TEST1 section.
70 @ CHECK: Name: .ARM.extab.TEST1
77 @ RELOC: Name: .rel.ARM.extab.TEST1
86 @ Check the .ARM.exidx.TEST1 section.
[all …]
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| D | eh-directive-section-comdat.s | 16 .section .TEST1,"axG",%progbits,func1,comdat
53 @ These are the section indexes of .TEST1, .ARM.extab.TEST1, .ARM.exidx.TEST1,
54 @ .rel.ARM.extab.TEST1, and .rel.ARM.exidx.TEST1.
63 @ Check the .TEST1 section
67 @ CHECK-NEXT: Name: .TEST1
81 @ Check the .ARM.extab.TEST1 section
85 @ CHECK-NEXT: Name: .ARM.extab.TEST1
98 @ CHECK-NEXT: Name: .rel.ARM.extab.TEST1
102 @ Check the .ARM.exidx.TEST1 section
106 @ CHECK-NEXT: Name: .ARM.exidx.TEST1
[all …]
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| D | eh-directive-section.s | 19 @ .TEST1 section
21 .section .TEST1
49 @ Check the .TEST1 section.
54 @ CHECK-NEXT: Name: .TEST1
61 @ Check the .ARM.extab.TEST1 section, the EXTAB of .TEST1 section.
64 @ CHECK: Name: .ARM.extab.TEST1
71 @ RELOC: Name: .rel.ARM.extab.TEST1
79 @ Check the.ARM.exidx.TEST1 section, the EXIDX of .TEST1 section.
82 @ CHECK: Name: .ARM.exidx.TEST1
85 @ This section should linked with .TEST1 section.
[all …]
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| D | eh-compact-pr1.s | 8 .section .TEST1
25 @ Check .TEST1 section
29 @ CHECK: Name: .TEST1
37 @ Check .ARM.extab.TEST1 section
40 @ CHECK: Name: .ARM.extab.TEST1
55 @ Check .ARM.exidx.TEST1 section
58 @ CHECK: Name: .ARM.exidx.TEST1
65 @ The first word should be relocated to .TEST1 section, and the second word
66 @ should be relocated to .ARM.extab.TEST1 section. Besides, there is
72 @ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0
[all …]
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| D | eh-directive-personality.s | 11 @ TEST1
13 .section .TEST1
26 @ CHECK: Name: .TEST1
32 @ CHECK: Name: .ARM.extab.TEST1
39 @ RELOC: Name: .rel.ARM.extab.TEST1
46 @ CHECK: Name: .ARM.exidx.TEST1
53 @ RELOC: Name: .rel.ARM.exidx.TEST1
55 @ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0
56 @ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
|
| D | eh-compact-pr0.s | 10 .section .TEST1
38 @ Check .TEST1 section
42 @ CHECK: Name: .TEST1
50 @ Check .ARM.exidx.TEST1 section
53 @ CHECK: Name: .ARM.exidx.TEST1
64 @ The first word should be relocated to .TEST1 section. Besides, there is
69 @ RELOC: Name: .rel.ARM.exidx.TEST1
72 @ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0
87 @ Check .ARM.exidx.TEST1 section
|
| D | eh-directive-handlerdata.s | 11 @ TEST1
13 .section .TEST1
25 @ CHECK: Name: .TEST1
32 @ CHECK: Name: .ARM.extab.TEST1
39 @ CHECK: Name: .ARM.exidx.TEST1
49 @ RELOC: Name: .rel.ARM.exidx.TEST1
52 @ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0
53 @ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
|
| /external/llvm/test/MC/AsmParser/ |
| D | directive_space.s | 8 # CHECK: TEST1:
10 TEST1: label
19 # CHECK: .space TEST0-TEST1
21 .space TEST0 - TEST1
|
| D | directive_org.s | 8 # CHECK: TEST1:
10 TEST1: label
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| D | directive_align.s | 8 # CHECK: TEST1:
10 TEST1: label
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| D | directive_set.s | 9 # CHECK: TEST1:
12 TEST1: label
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| /external/llvm/test/Other/ |
| D | FileCheck-space.txt | 1 RUN: printf "a\nb" | FileCheck %s -check-prefix=TEST1
5 TEST1:a
6 TEST1-NEXT:b
|
| /external/swiftshader/third_party/LLVM/test/MC/AsmParser/ |
| D | directive_org.s | 8 # CHECK: TEST1:
10 TEST1: label
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| D | directive_set.s | 8 # CHECK: TEST1:
10 TEST1: label
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| D | directive_space.s | 8 # CHECK: TEST1:
10 TEST1: label
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| D | directive_align.s | 8 # CHECK: TEST1:
10 TEST1: label
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| D | directive_fill.s | 8 # CHECK: TEST1:
11 TEST1: label
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| /external/clang/test/CodeGenObjCXX/ |
| D | property-reference.mm | 44 // CHECK: [[SELF:%.*]] = alloca [[TEST1:%.*]]*, align 8
45 // CHECK: [[T0:%.*]] = load [[TEST1]]*, [[TEST1]]** [[SELF]]
46 // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST1]]* [[T0]] to i8*
|