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Searched refs:TGSI_OPCODE_DIV (Results 1 – 13 of 13) sorted by relevance

/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_util.c187 case TGSI_OPCODE_DIV: in tgsi_util_get_inst_usage_mask()
Dtgsi_info.c110 { 1, 2, 0, 0, 0, 0, COMP, "DIV", TGSI_OPCODE_DIV },
Dtgsi_exec.c3825 case TGSI_OPCODE_DIV: in exec_instruction()
/external/mesa3d/src/gallium/include/pipe/
Dp_shader_tokens.h327 #define TGSI_OPCODE_DIV 70 macro
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi.c214 case TGSI_OPCODE_DIV: in lp_build_tgsi_inst_llvm()
Dlp_bld_tgsi_action.c519 TGSI_OPCODE_DIV, abs_x, ex2_flr_log_abs_x); in log_emit()
1168 TGSI_OPCODE_DIV, in log_emit_cpu()
1572 bld_base->op_actions[TGSI_OPCODE_DIV].emit = div_emit_cpu; in lp_set_default_actions_cpu()
Dlp_bld_tgsi_aos.c827 case TGSI_OPCODE_DIV: in lp_emit_instruction_aos()
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_setup_tgsi_llvm.c603 TGSI_OPCODE_DIV, arg, src_w); in txp_fetch_args()
1122 bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem; in radeon_llvm_context_init()
1123 bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div"; in radeon_llvm_context_init()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dradeonsi_shader.c614 TGSI_OPCODE_DIV, in tex_fetch_args()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c5313 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5487 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5661 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_from_tgsi.cpp1755 case TGSI_OPCODE_DIV: in handleInstruction()
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_insn.c2570 case TGSI_OPCODE_DIV: in svga_emit_instruction()
/external/mesa3d/src/mesa/state_tracker/
Dst_glsl_to_tgsi.cpp1509 emit(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]); in visit()