| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 43 UXTX, enumerator
63 case AArch64_AM::UXTX: return "uxtx"; in getShiftExtendName()
130 case 3: return AArch64_AM::UXTX; in getExtendType()
157 case AArch64_AM::UXTX: return 3; break; in getExtendEncoding()
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.cc | 322 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
335 ((extend_ == UXTX) || (extend_ == SXTX) || in IsPlainRegister()
362 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
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| D | disasm-aarch64.cc | 165 const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext" in VisitAddSubExtended()
168 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; in VisitAddSubExtended()
4744 (instr->GetExtendMode() == UXTX))) { in SubstituteExtendField()
4783 if (!((ext == UXTX) && (shift == 0))) { in SubstituteLSRegOffsetField()
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| D | macro-assembler-aarch64.cc | 855 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in LogicalMacro()
1747 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in AddSubWithCarryMacro()
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| D | constants-aarch64.h | 288 UXTX = 3, enumerator
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| D | simulator-aarch64.cc | 415 case UXTX: in ExtendValue()
1287 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | assembler-aarch64.cc | 4202 case UXTX: in EmitExtendShift()
4286 ext = UXTX; in LoadStoreMemOperand()
|
| /external/v8/src/arm64/ |
| D | disasm-arm64.cc | 144 const char *form = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
146 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
1648 (instr->ExtendMode() == UXTX))) { in SubstituteExtendField()
1681 if (!((ext == UXTX) && (shift == 0))) { in SubstituteLSRegOffsetField()
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| D | assembler-arm64-inl.h | 352 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
383 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
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| D | constants-arm64.h | 342 UXTX = 3, enumerator
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| D | assembler-arm64.cc | 2501 case UXTX: in EmitExtendShift()
2576 ext = UXTX; in LoadStore()
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| D | simulator-arm64.cc | 995 case UXTX: in ExtendValue()
1615 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 362 UXTX, enumerator
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1104 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1108 ExtType == AArch64_AM::UXTX) || in printArithExtend()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 991 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtend()
1001 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX; in isExtend64()
1007 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtendLSL64()
1569 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
2392 .Case("uxtx", AArch64_AM::UXTX) in tryParseOptionalShiftExtend()
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 638 __ Orr(x9, x0, Operand(x1, UXTX, 3)); in TEST()
732 __ Orn(x9, x0, Operand(x1, UXTX, 3)); in TEST()
799 __ And(x9, x0, Operand(x1, UXTX, 3)); in TEST()
937 __ Bic(x9, x0, Operand(x1, UXTX, 3)); in TEST()
1061 __ Eor(x9, x0, Operand(x1, UXTX, 3)); in TEST()
1128 __ Eon(x9, x0, Operand(x1, UXTX, 3)); in TEST()
8613 __ Adc(x13, x1, Operand(x2, UXTX, 4)); in TEST()
8625 __ Adc(x23, x1, Operand(x2, UXTX, 4)); in TEST()
13313 __ adds(xzr, x0, Operand(x1, UXTX)); in TEST()
13314 __ adds(xzr, x1, Operand(xzr, UXTX)); in TEST()
[all …]
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| D | test-disasm-aarch64.cc | 429 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4"); in TEST()
441 COMPARE(cmn(sp, Operand(xzr, UXTX, 3)), "cmn sp, xzr, lsl #3"); in TEST()
455 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4"); in TEST()
467 COMPARE(cmp(sp, Operand(xzr, UXTX, 3)), "cmp sp, xzr, lsl #3"); in TEST()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 1781 // UXTX and SXTX only.
1808 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1811 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1855 // UXTX and SXTX only.
1913 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
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| D | AArch64InstrInfo.cpp | 1448 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val); in isScaledAddr()
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| D | AArch64ISelDAGToDAG.cpp | 596 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX); in SelectArithExtendedRegister()
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