/external/libmojo/mojo/public/interfaces/bindings/tests/ |
D | test_structs.mojom | 206 const int32 V10 = -2147483648; 231 int32 f10 = V10; 262 const uint64 V10 = 1234567890123456; 278 uint64 f10 = V10;
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/external/sonivox/arm-wt-22k/vectors/ |
D | abba.imy | 8 VOLUME:V10
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
D | PPCBaseInfo.h | 41 case R10: case X10: case F10: case V10: case CR2EQ: return 10; in getPPCRegisterNumbering()
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCCallingConv.td | 51 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>> 109 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
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D | PPCRegisterInfo.td | 180 def V10 : VR<10, "v10">, DwarfRegNum<[87, 87]>; 299 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
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D | PPCInstr64Bit.td | 71 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 97 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
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D | PPCFrameLowering.cpp | 43 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
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D | PPCInstrInfo.td | 438 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 463 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
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D | PPCISelLowering.cpp | 1876 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_Darwin() 3135 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_Darwin()
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/external/libmojo/mojo/public/js/ |
D | struct_unittests.js | 211 expect(decodedStruct.f10).toEqual(testStructs.IntegerNumberValues.V10); 236 expect(decodedStruct.f10).toEqual(testStructs.UnsignedNumberValues.V10);
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 70 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
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D | HexagonRegisterInfo.td | 188 def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>; 274 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11,
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D | HexagonISelLowering.cpp | 324 Hexagon::V10, Hexagon::V11, in CC_HexagonVector()
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
D | SystemZMCTargetDesc.cpp | 104 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
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/external/clang/test/Parser/ |
D | MicrosoftExtensions.cpp | 320 …__declspec(property(get=GetV,)) int V10; // expected-error {{expected 'get' or 'put' in property d…
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/external/llvm/test/Transforms/SLPVectorizer/X86/ |
D | insert-element-build-vector.ll | 319 ; CHECK-DAG: %[[V10:.+]] = extractelement <2 x double> %[[V9]], i32 0 320 ; CHECK-DAG: %[[I3:.+]] = insertelement <4 x double> %i2, double %[[V10]], i32 1
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/external/llvm/lib/Transforms/InstCombine/ |
D | InstCombineCalls.cpp | 698 APInt V10 = CI10->getValue(); in simplifyX86insertq() local 701 V10 = V10.zextOrTrunc(Length).zextOrTrunc(64).shl(Index); in simplifyX86insertq() 702 APInt Val = V00 | V10; in simplifyX86insertq()
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/external/llvm/lib/Target/PowerPC/Disassembler/ |
D | PPCDisassembler.cpp | 95 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
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/external/llvm/lib/Target/PowerPC/ |
D | PPCCallingConv.td | 192 V8, V9, V10, V11, V12, V13]>>>,
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D | PPCRegisterInfo.td | 292 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
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D | PPCFrameLowering.cpp | 35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
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D | PPCISelLowering.cpp | 3154 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_64SVR4() 3575 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_Darwin() 3979 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in needStackSlotPassParameters() 5035 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_64SVR4() 5742 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_Darwin()
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/external/llvm/lib/Target/Hexagon/Disassembler/ |
D | HexagonDisassembler.cpp | 510 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, in DecodeVectorRegsRegisterClass()
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
D | PPCAsmParser.cpp | 89 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
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