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Searched refs:V10 (Results 1 – 24 of 24) sorted by relevance

/external/libmojo/mojo/public/interfaces/bindings/tests/
Dtest_structs.mojom206 const int32 V10 = -2147483648;
231 int32 f10 = V10;
262 const uint64 V10 = 1234567890123456;
278 uint64 f10 = V10;
/external/sonivox/arm-wt-22k/vectors/
Dabba.imy8 VOLUME:V10
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h41 case R10: case X10: case F10: case V10: case CR2EQ: return 10; in getPPCRegisterNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCCallingConv.td51 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
109 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
DPPCRegisterInfo.td180 def V10 : VR<10, "v10">, DwarfRegNum<[87, 87]>;
299 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
DPPCInstr64Bit.td71 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
97 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
DPPCFrameLowering.cpp43 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
DPPCInstrInfo.td438 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
463 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
DPPCISelLowering.cpp1876 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_Darwin()
3135 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_Darwin()
/external/libmojo/mojo/public/js/
Dstruct_unittests.js211 expect(decodedStruct.f10).toEqual(testStructs.IntegerNumberValues.V10);
236 expect(decodedStruct.f10).toEqual(testStructs.UnsignedNumberValues.V10);
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp70 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
DHexagonRegisterInfo.td188 def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>;
274 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11,
DHexagonISelLowering.cpp324 Hexagon::V10, Hexagon::V11, in CC_HexagonVector()
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.cpp104 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
/external/clang/test/Parser/
DMicrosoftExtensions.cpp320 …__declspec(property(get=GetV,)) int V10; // expected-error {{expected 'get' or 'put' in property d…
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dinsert-element-build-vector.ll319 ; CHECK-DAG: %[[V10:.+]] = extractelement <2 x double> %[[V9]], i32 0
320 ; CHECK-DAG: %[[I3:.+]] = insertelement <4 x double> %i2, double %[[V10]], i32 1
/external/llvm/lib/Transforms/InstCombine/
DInstCombineCalls.cpp698 APInt V10 = CI10->getValue(); in simplifyX86insertq() local
701 V10 = V10.zextOrTrunc(Length).zextOrTrunc(64).shl(Index); in simplifyX86insertq()
702 APInt Val = V00 | V10; in simplifyX86insertq()
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp95 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td192 V8, V9, V10, V11, V12, V13]>>>,
DPPCRegisterInfo.td292 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
DPPCFrameLowering.cpp35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
DPPCISelLowering.cpp3154 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_64SVR4()
3575 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_Darwin()
3979 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in needStackSlotPassParameters()
5035 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_64SVR4()
5742 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_Darwin()
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp510 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, in DecodeVectorRegsRegisterClass()
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp89 PPC::V8, PPC::V9, PPC::V10, PPC::V11,