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Searched refs:V5 (Results 1 – 25 of 80) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/
Dldr_ext.ll1 ; RUN: llc < %s -march=thumb | FileCheck %s -check-prefix=V5
7 ; V5: ldrb
16 ; V5: ldrh
25 ; V5: ldrb
26 ; V5: lsls
27 ; V5: asrs
37 ; V5: ldrh
38 ; V5: lsls
39 ; V5: asrs
49 ; V5: movs r0, #0
[all …]
/external/llvm/test/CodeGen/Thumb/
Dldr_ext.ll1 ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=V5
7 ; V5: ldrb
16 ; V5: ldrh
25 ; V5: ldrb
26 ; V5: lsls
27 ; V5: asrs
37 ; V5: ldrh
38 ; V5: lsls
39 ; V5: asrs
49 ; V5: movs r0, #0
[all …]
/external/eigen/unsupported/Eigen/CXX11/src/Tensor/
DTensorDimensions.h154 template <std::size_t V1=0, std::size_t V2=0, std::size_t V3=0, std::size_t V4=0, std::size_t V5=0>…
155 …ro_size<V3>::type, typename non_zero_size<V4>::type, typename non_zero_size<V5>::type >::type Base;
224 template <std::size_t V1, std::size_t V2, std::size_t V3, std::size_t V4, std::size_t V5>
225 EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::size_t array_prod(const Sizes<V1, V2, V3, V4, V5>&) {
226 return Sizes<V1, V2, V3, V4, V5>::total_size;
385 …e_t V2, std::size_t V3, std::size_t V4, std::size_t V5> struct array_size<const Sizes<V1,V2,V3,V4,…
386 static const size_t value = Sizes<V1,V2,V3,V4,V5>::count;
388 …size_t V2, std::size_t V3, std::size_t V4, std::size_t V5> struct array_size<Sizes<V1,V2,V3,V4,V5>…
389 static const size_t value = Sizes<V1,V2,V3,V4,V5>::count;
391 …3, std::size_t V4, std::size_t V5> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::size_t array_get(con…
[all …]
/external/llvm/test/Transforms/SimplifyCFG/
DPhiEliminate2.ll13 %V5 = sext i16 %V3 to i32
16 %V6 = phi i32 [ %V5, %else ], [ %V4, %then ]
22 ; CHECK-NEXT: %V5 = sext i16 %V3 to i32
24 ; CHECK-NEXT: %V6 = select i1 %C, i32 %V4, i32 %V5, !prof !0, !unpredictable !1
/external/llvm/unittests/Support/
DAlignOfTest.cpp70 struct V5 : V4, V3 { double z; struct
71 ~V5() override;
77 struct V8 : V5, virtual V6, V7 { double zz;
87 V5::~V5() {} in ~V5()
149 [AlignOf<V5>::Alignment > 0]
189 EXPECT_LE(alignOf<V1>(), alignOf<V5>()); in TEST()
271 EXPECT_EQ(alignOf<V5>(), alignOf<AlignedCharArrayUnion<V5> >()); in TEST()
336 EXPECT_EQ(sizeof(V5), sizeof(AlignedCharArrayUnion<V5>)); in TEST()
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dldrd.ll2 ; RUN: llc < %s -mtriple=armv5-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V5
14 ;V5: ldr r{{[0-9]+}}, [r2]
15 ;V5: ldr r{{[0-9]+}}, [r2, #4]
/external/llvm/test/CodeGen/ARM/
DMachO-subtypes.ll7 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
9 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
11 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
13 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
15 ; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5
61 ; CHECK-V5: CpuSubType: CPU_SUBTYPE_ARM_V5 (0x7)
Dpr18364-movw.ll1 ; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
9 ; V5-NOT: movw
25 ; V5-NOT: movw
/external/llvm/lib/Target/Hexagon/
DHexagonSubtarget.h42 V4, V5, V55, V60 enumerator
90 bool hasV5TOps() const { return getHexagonArchVersion() >= V5; } in hasV5TOps()
91 bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; } in hasV5TOpsOnly()
DHexagonRegisterInfo.cpp70 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
125 case HexagonSubtarget::V5: in getCalleeSavedRegs()
/external/llvm/test/MC/AArch64/
Dcase-insen-reg-names.s4 fadd V0.2d, V5.2d, V6.2d
5 fadd v0.2d, V5.2d, v6.2d
/external/swiftshader/third_party/LLVM/test/Transforms/SimplifyCFG/
DPhiEliminate2.ll10 %V5 = sext i16 %V3 to i32 ; <i32> [#uses=1]
13 %V6 = phi i32 [ %V5, %else ], [ %V4, %then ] ; <i32> [#uses=0]
/external/llvm/test/MC/Hexagon/
Delf-flags.s2 …j %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V5 %s
7 # CHECK-V5: Flags: 0x4
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dthumb-diagnostics.s4 @ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
20 @ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
21 @ CHECK-ERRORS-V5: mov r2, r3
22 @ CHECK-ERRORS-V5: ^
/external/libmojo/mojo/public/interfaces/bindings/tests/
Dtest_structs.mojom172 const float V5 = float.NAN;
183 float f5 = V5;
200 const int16 V5 = -32768; // ...
225 int16 f5 = V5;
254 const uint16 V5 = 0xFFFF;
271 uint16 f5 = V5;
/external/clang/test/Parser/
Drecovery.cpp151 enum class EC3 { V0 = 0, V5 = 5 }; // expected-note {{declared here}}
167 …case EC3::V5:: break; // expected-error{{'V5' cannot appear before '::' because it is not a class,…
/external/clang/test/SemaCXX/
DMicrosoftExtensions.cpp259 __declspec(property(get=GetV, put=SetV)) int V5; member
270 int k = sp.V5; in TestProperty()
271 sp.V5 = k++; in TestProperty()
/external/llvm/test/CodeGen/Hexagon/
Dopt-fabs.ll2 ; Optimize fabsf to clrbit in V5.
Ddadd.ll2 ; Check that we generate double precision floating point add in V5.
Dfadd.ll2 ; Check that we generate sp floating point add in V5.
Ddmul.ll2 ; Check that we generate double precision floating point multiply in V5.
Dfmul.ll2 ; Check that we generate single precision floating point multiply in V5.
Dfsub.ll2 ; Check that we generate sp floating point subtract in V5.
Ddsub.ll2 ; Check that we generate double precision floating point subtract in V5.
Dopt-fneg.ll2 ; Optimize fneg to togglebit in V5.

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