Searched refs:VOP2 (Results 1 – 12 of 12) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstructions.td | 44 // VOP2 Instructions
89 // are VOP2 on SI and VOP3 on VI.
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| D | SIInstrFormats.td | 32 field bits<1> VOP2 = 0;
68 let TSFlags{11} = VOP2;
142 let VOP2 = 1;
648 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
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| D | SIDefines.h | 29 VOP2 = 1 << 11, enumerator
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| D | SIInstrInfo.h | 256 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
260 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
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| D | SIInstrInfo.td | 46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
1141 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1191 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1221 // VOP2 without modifiers
1786 VOP2 <op.SI, outs, ins, opName#asm, []>,
1794 VOP2 <op.VI, outs, ins, opName#asm, []>,
2072 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
2080 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
2228 // A VOP2 instruction that is VOP3-only on VI.
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| D | SIInstructions.td | 1478 // VOP2 Instructions
2497 // VOP2 Patterns
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| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 101 VOP1, VOP2, VOP3, VOPC Instructions
107 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 50 VOP2 = 13, enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstrInfo.td | 384 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
397 let EncodingType = 13; // SIInstrEncodingType::VOP2
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| D | SIInstrFormats.td | 72 VOP2 <
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| D | SIInstructions.td | 670 def V_CNDMASK_B32 : VOP2 <0x00000000, (outs VReg_32:$dst),
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2683 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
2731 case SIInstrFlags::VOP2: { in cvtSDWA()
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