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Searched refs:VR (Results 1 – 25 of 211) sorted by relevance

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/external/libyuv/files/source/
Drow_common.cc993 #define VR -102 /* round(-1.596 * 64) */ macro
998 #define BR (VR * 128 + YGB)
1002 {-UB, -VR, -UB, -VR, -UB, -VR, -UB, -VR},
1003 {-UB, -VR, -UB, -VR, -UB, -VR, -UB, -VR},
1009 {-VR, -UB, -VR, -UB, -VR, -UB, -VR, -UB},
1010 {-VR, -UB, -VR, -UB, -VR, -UB, -VR, -UB},
1017 {-UB, -UB, -UB, -UB, -VR, -VR, -VR, -VR, 0, 0, 0, 0, 0, 0, 0, 0},
1022 {-VR, -VR, -VR, -VR, -UB, -UB, -UB, -UB, 0, 0, 0, 0, 0, 0, 0, 0},
1032 {0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR,
1033 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR},
[all …]
/external/libvpx/libvpx/third_party/libyuv/source/
Drow_common.cc984 #define VR -102 /* round(-1.596 * 64) */ macro
989 #define BR (VR * 128 + YGB)
993 { -UB, -VR, -UB, -VR, -UB, -VR, -UB, -VR },
994 { -UB, -VR, -UB, -VR, -UB, -VR, -UB, -VR },
1001 { -VR, -UB, -VR, -UB, -VR, -UB, -VR, -UB },
1002 { -VR, -UB, -VR, -UB, -VR, -UB, -VR, -UB },
1010 { -UB, -UB, -UB, -UB, -VR, -VR, -VR, -VR, 0, 0, 0, 0, 0, 0, 0, 0 },
1016 { -VR, -VR, -VR, -VR, -UB, -UB, -UB, -UB, 0, 0, 0, 0, 0, 0, 0, 0 },
1027 { 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR,
1028 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR, 0, VR },
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp194 unsigned operator[](unsigned VR) const { in operator []()
195 const_iterator F = find(VR); in operator []()
251 const BitTracker::RegisterCell &lookup(unsigned VR) { in lookup()
252 unsigned RInd = TargetRegisterInfo::virtReg2Index(VR); in lookup()
258 CP = CVect[RInd] = &BT.lookup(VR); in lookup()
362 void insert(unsigned VR);
363 void remove(unsigned VR);
410 void OrderedRegisterList::insert(unsigned VR) { in insert() argument
411 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord); in insert()
413 Seq.push_back(VR); in insert()
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.td50 // VR - One of the 32 128-bit vector registers
51 class VR<bits<5> num, string n> : PPCReg<n> {
170 def V0 : VR< 0, "v0">, DwarfRegNum<[77, 77]>;
171 def V1 : VR< 1, "v1">, DwarfRegNum<[78, 78]>;
172 def V2 : VR< 2, "v2">, DwarfRegNum<[79, 79]>;
173 def V3 : VR< 3, "v3">, DwarfRegNum<[80, 80]>;
174 def V4 : VR< 4, "v4">, DwarfRegNum<[81, 81]>;
175 def V5 : VR< 5, "v5">, DwarfRegNum<[82, 82]>;
176 def V6 : VR< 6, "v6">, DwarfRegNum<[83, 83]>;
177 def V7 : VR< 7, "v7">, DwarfRegNum<[84, 84]>;
[all …]
/external/compiler-rt/lib/profile/
DInstrProfilingMergeFile.c29 ValueProfRecord *VR = getFirstValueProfRecord(SrcValueProfData); in lprofMergeValueProfData() local
31 VData = getValueProfRecordValueData(VR); in lprofMergeValueProfData()
32 for (S = 0; S < VR->NumValueSites; S++) { in lprofMergeValueProfData()
33 uint8_t NV = VR->SiteCountArray[S]; in lprofMergeValueProfData()
39 VR = getValueProfRecordNext(VR); in lprofMergeValueProfData()
/external/llvm/lib/ProfileData/
DInstrProf.cpp576 ValueProfRecord *VR = getFirstValueProfRecord(this); in deserializeTo() local
578 VR->deserializeTo(Record, VMap); in deserializeTo()
579 VR = getValueProfRecordNext(VR); in deserializeTo()
604 ValueProfRecord *VR = getFirstValueProfRecord(this); in checkIntegrity() local
606 if (VR->Kind > IPVK_Last) in checkIntegrity()
608 VR = getValueProfRecordNext(VR); in checkIntegrity()
609 if ((char *)VR - (char *)this > (ptrdiff_t)TotalSize) in checkIntegrity()
648 ValueProfRecord *VR = getFirstValueProfRecord(this); in swapBytesToHost() local
650 VR->swapBytes(Endianness, getHostEndianness()); in swapBytesToHost()
651 VR = getValueProfRecordNext(VR); in swapBytesToHost()
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/external/clang/lib/StaticAnalyzer/Checkers/
DUndefCapturedBlockVarChecker.cpp68 const VarRegion *VR = I.getCapturedRegion(); in checkPostStmt() local
69 const VarDecl *VD = VR->getDecl(); in checkPostStmt()
93 *V, VR, /*EnableNullFPSuppression*/ false)); in checkPostStmt()
DStackAddrEscapeChecker.cpp76 else if (const VarRegion *VR = dyn_cast<VarRegion>(R)) { in genName() local
78 << VR->getString() << '\''; in genName()
79 range = VR->getDecl()->getSourceRange(); in genName()
245 const VarRegion *VR = cast<VarRegion>(cb.V[i].first->getBaseRegion()); in checkEndFunction() local
246 os << *VR->getDecl() in checkEndFunction()
DMacOSXAPIChecker.cpp86 if (const VarRegion *VR = dyn_cast<VarRegion>(R)) in CheckDispatchOnce() local
87 os << " the local variable '" << VR->getDecl()->getName() << '\''; in CheckDispatchOnce()
DNSErrorChecker.cpp193 if (const VarRegion *VR = R->getAs<VarRegion>()) in parameterTypeFromSVal() local
195 stackReg = dyn_cast<StackArgumentsSpaceRegion>(VR->getMemorySpace())) in parameterTypeFromSVal()
197 return VR->getValueType(); in parameterTypeFromSVal()
DMallocChecker.cpp1546 const VarRegion *VR = dyn_cast<VarRegion>(MR); in SummarizeRegion() local
1548 if (VR) in SummarizeRegion()
1549 VD = VR->getDecl(); in SummarizeRegion()
1561 const VarRegion *VR = dyn_cast<VarRegion>(MR); in SummarizeRegion() local
1563 if (VR) in SummarizeRegion()
1564 VD = VR->getDecl(); in SummarizeRegion()
1576 const VarRegion *VR = dyn_cast<VarRegion>(MR); in SummarizeRegion() local
1578 if (VR) in SummarizeRegion()
1579 VD = VR->getDecl(); in SummarizeRegion()
2036 const VarRegion* VR = MR->getBaseRegion()->getAs<VarRegion>(); in getAllocationSite() local
[all …]
/external/clang/lib/StaticAnalyzer/Core/
DSymbolManager.cpp430 if (const VarRegion *VR = dyn_cast<VarRegion>(MR)) in isLiveRegion() local
431 return isLive(VR, true); in isLiveRegion()
520 bool SymbolReaper::isLive(const VarRegion *VR, bool includeStoreBindings) const{ in isLive() argument
521 const StackFrameContext *VarContext = VR->getStackFrame(); in isLive()
535 if (LCtx->getAnalysis<RelaxedLiveVariables>()->isLive(Loc, VR->getDecl())) in isLive()
542 const_cast<SymbolReaper*>(this)->includedRegionCache[VR]; in isLive()
551 reapedStore.getStoreManager().includedInBindings(store, VR); in isLive()
DMemRegion.cpp676 const VarRegion *const VR = dyn_cast<VarRegion>(this->getBaseRegion()); in sourceRange() local
685 else if (VR) { in sourceRange()
686 return VR->getDecl()->getSourceRange(); in sourceRange()
810 if (const VarRegion *VR = dyn_cast<VarRegion>(I.getOriginalRegion())) in getStackOrCaptureRegionForDeclContext() local
811 if (VR->getDecl() == VD) in getStackOrCaptureRegionForDeclContext()
1420 const VarRegion *VR = nullptr; in getCaptureRegions() local
1424 VR = MemMgr.getVarRegion(VD, this); in getCaptureRegions()
1429 VR = MemMgr.getVarRegion(VD, LC); in getCaptureRegions()
1430 OriginalVR = VR; in getCaptureRegions()
1433 VR = MemMgr.getVarRegion(VD, MemMgr.getUnknownRegion()); in getCaptureRegions()
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DBugReporterVisitors.cpp423 static bool isInitializationOfVar(const ExplodedNode *N, const VarRegion *VR) { in isInitializationOfVar() argument
432 if (DS->getSingleDecl() != VR->getDecl()) in isInitializationOfVar()
435 const MemSpaceRegion *VarSpace = VR->getMemorySpace(); in isInitializationOfVar()
441 assert(VR->getDecl()->isStaticLocal() && "non-static stackless VarRegion"); in isInitializationOfVar()
445 assert(VR->getDecl()->hasLocalStorage()); in isInitializationOfVar()
463 if (const VarRegion *VR = dyn_cast<VarRegion>(R)) { in VisitNode() local
464 if (isInitializationOfVar(Pred, VR)) { in VisitNode()
466 InitE = VR->getDecl()->getInit(); in VisitNode()
509 if (const VarRegion *VR = dyn_cast<VarRegion>(R)) { in VisitNode() local
510 const ParmVarDecl *Param = cast<ParmVarDecl>(VR->getDecl()); in VisitNode()
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/external/valgrind/VEX/priv/
Dhost_ppc_defs.h56 #define VR(_mode64, _enc, _ix64, _ix32) \ macro
99 ST_IN HReg hregPPC_VR20 ( Bool mode64 ) { return VR (mode64, 20, 31, 33); } in hregPPC_VR20()
100 ST_IN HReg hregPPC_VR21 ( Bool mode64 ) { return VR (mode64, 21, 32, 34); } in hregPPC_VR21()
101 ST_IN HReg hregPPC_VR22 ( Bool mode64 ) { return VR (mode64, 22, 33, 35); } in hregPPC_VR22()
102 ST_IN HReg hregPPC_VR23 ( Bool mode64 ) { return VR (mode64, 23, 34, 36); } in hregPPC_VR23()
103 ST_IN HReg hregPPC_VR24 ( Bool mode64 ) { return VR (mode64, 24, 35, 37); } in hregPPC_VR24()
104 ST_IN HReg hregPPC_VR25 ( Bool mode64 ) { return VR (mode64, 25, 36, 38); } in hregPPC_VR25()
105 ST_IN HReg hregPPC_VR26 ( Bool mode64 ) { return VR (mode64, 26, 37, 39); } in hregPPC_VR26()
106 ST_IN HReg hregPPC_VR27 ( Bool mode64 ) { return VR (mode64, 27, 38, 40); } in hregPPC_VR27()
112 ST_IN HReg hregPPC_VR29 ( Bool mode64 ) { return VR (mode64, 29, 43, 45); } in hregPPC_VR29()
[all …]
/external/llvm/lib/Target/PowerPC/
DREADME_P9.txt57 VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].byte[3])
65 VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].hword[1])
73 VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].byte[7])
81 VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].hword[3])
89 VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].word[1])
122 sh ← VR[VRB].byte[i].bit[5:7]
123 VR[VRT].byte[i] ← src.byte[i:i+1].bit[sh:sh+7]
126 VR[VRT].byte[i] is composed of 2 bytes from src.byte[i:i+1]
DPPCRegisterInfo.td66 // VR - One of the 32 128-bit vector registers
67 class VR<VF SubReg, string n> : PPCReg<n> {
84 class VSRH<VR SubReg, string n> : PPCReg<n> {
132 def V#Index : VR<!cast<VF>("VF"#Index), "v"#Index>,
142 def VSH#Index : VSRH<!cast<VR>("V"#Index), "vs" # !add(Index, 32)>,
143 DwarfRegAlias<!cast<VR>("V"#Index)>;
/external/clang/test/SemaCXX/
Daddr-of-overloaded-function.cpp217 void VR() volatile __restrict {}; in VR() function
229 …X = &Qualifiers::VR; // expected-error-re{{assigning to 'void (test1::Qualifiers::*)(){{( __attrib… in QualifierTest()
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp155 unsigned VR = MRI.createVirtualRegister(RC); in expandLoadCCond() local
158 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
160 .addReg(VR, RegState::Kill); in expandLoadCCond()
170 unsigned VR = MRI.createVirtualRegister(RC); in expandStoreCCond() local
173 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
175 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
516 unsigned VR = MF.getRegInfo().createVirtualRegister(RC); in emitPrologue() local
521 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign); in emitPrologue()
522 BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); in emitPrologue()
/external/llvm/test/CodeGen/AMDGPU/
Duint_to_fp.i64.ll24 ; GCN: v_add_i32_e32 [[VR:v[0-9]+]]
25 ; GCN: {{buffer|flat}}_store_dword {{.*}}[[VR]]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineSSAUpdater.h43 unsigned VR; variable
/external/llvm/include/llvm/CodeGen/
DMachineSSAUpdater.h44 unsigned VR; variable
/external/swiftshader/third_party/LLVM/include/llvm/Support/
DPatternMatch.h211 Class *&VR; member
212 bind_ty(Class *&V) : VR(V) {} in bind_ty()
217 VR = CV; in match()
248 uint64_t &VR; member
249 bind_const_intval_ty(uint64_t &V) : VR(V) {} in bind_const_intval_ty()
255 VR = CV->getZExtValue(); in match()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineSSAUpdater.cpp56 VR = V; in Initialize()
57 VRC = MRI->getRegClass(VR); in Initialize()
/external/llvm/lib/CodeGen/
DMachineSSAUpdater.cpp57 VR = V; in Initialize()
58 VRC = MRI->getRegClass(VR); in Initialize()

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