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Searched refs:VR1 (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp189 unsigned VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() local
198 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
199 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
214 unsigned VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() local
221 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
222 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
246 unsigned VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() local
255 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
257 .addReg(VR1, RegState::Kill); in expandCopyACC()
DMipsSEISelLowering.cpp2960 unsigned VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
2961 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
2969 .addReg(VR1) in emitBPOSGE32()
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp201 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
202 return operator[](VR1) < operator[](VR2); in operator ()()
277 bool operator() (unsigned VR1, unsigned VR2) const;
293 bool operator() (unsigned VR1, unsigned VR2) const;
303 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
313 if (VR1 == VR2) in operator ()()
316 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
327 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
331 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
332 if (VR1 == VR2) in operator ()()
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