Searched refs:VRC (Results 1 – 10 of 10) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineSSAUpdater.cpp | 57 VRC = MRI->getRegClass(VR); in Initialize()
151 VRC, MRI, TII); in GetValueInMiddleOfBlock()
187 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
305 Updater->VRC, Updater->MRI, in GetUndefVal()
316 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
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| /external/llvm/lib/CodeGen/ |
| D | MachineSSAUpdater.cpp | 58 VRC = MRI->getRegClass(VR); in Initialize()
152 VRC, MRI, TII); in GetValueInMiddleOfBlock()
188 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
289 Updater->VRC, Updater->MRI, in GetUndefVal()
300 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineSSAUpdater.h | 46 const TargetRegisterClass *VRC; variable
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineSSAUpdater.h | 47 const TargetRegisterClass *VRC; variable
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1889 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove() local
1890 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) in legalizeOpWithMove()
1891 VRC = &AMDGPU::VReg_64RegClass; in legalizeOpWithMove()
1893 VRC = &AMDGPU::VGPR_32RegClass; in legalizeOpWithMove()
1895 unsigned Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
2168 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg); in readlaneVGPRToSGPR() local
2169 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
2171 unsigned SubRegs = VRC->getSize() / 4; in readlaneVGPRToSGPR()
2231 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; in legalizeOperands() local
2239 VRC = OpRC; in legalizeOperands()
[all …]
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| D | SIRegisterInfo.h | 127 const TargetRegisterClass *VRC) const;
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| D | SIRegisterInfo.cpp | 750 const TargetRegisterClass *VRC) const { in getEquivalentSGPRClass()
751 switch (VRC->getSize()) { in getEquivalentSGPRClass()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 402 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local
403 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
407 if (RC && RC != VRC) in ConstrainForSubReg()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 446 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local
447 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
451 if (RC && RC != VRC) in ConstrainForSubReg()
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| /external/llvm/lib/Target/PowerPC/ |
| D | p9-instrs.txt | 393 [PO VRT VRA VRB VRC XO] vpermr
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