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Searched refs:VREG (Results 1 – 7 of 7) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dllvm.AMDGPU.bfe.i32.ll88 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
89 ; SI: buffer_store_dword [[VREG]],
183 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
184 ; SI: buffer_store_dword [[VREG]],
195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
196 ; SI: buffer_store_dword [[VREG]],
207 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
208 ; SI: buffer_store_dword [[VREG]],
219 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
220 ; SI: buffer_store_dword [[VREG]],
[all …]
Dllvm.AMDGPU.bfe.u32.ll195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
196 ; SI: buffer_store_dword [[VREG]],
331 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
332 ; SI: buffer_store_dword [[VREG]],
343 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
344 ; SI: buffer_store_dword [[VREG]],
355 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
356 ; SI: buffer_store_dword [[VREG]],
367 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
368 ; SI: buffer_store_dword [[VREG]],
[all …]
Dtrunc-store-i1.ll8 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
9 ; SI: buffer_store_byte [[VREG]],
27 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
28 ; SI: buffer_store_byte [[VREG]],
/external/llvm/test/CodeGen/PowerPC/
Dppc32-pic.ll21 ; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30)
22 ; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
Dppc32-pic-large.ll24 ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
25 ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
/external/llvm/test/CodeGen/SystemZ/
Dvec-args-05.ll23 ; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
24 ; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
/external/vixl/src/aarch64/
Doperands-aarch64.cc182 #define VREG(n) v##n, macro
183 const VRegister VRegister::vregisters[] = {AARCH64_REGISTER_CODE_LIST(VREG)};
184 #undef VREG