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Searched refs:VRM (Results 1 – 25 of 41) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DVirtRegRewriter.cpp93 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM, in runOnMachineFunction()
118 if (!VRM.hasPhys(reg)) in runOnMachineFunction()
120 unsigned pReg = VRM.getPhys(reg); in runOnMachineFunction()
424 VirtRegMap &VRM);
442 VirtRegMap &VRM) { in GetRegForReload() argument
447 Rejected, RegKills, KillOps, VRM); in GetRegForReload()
679 VirtRegMap &VRM) { in ReMaterialize() argument
680 MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg); in ReMaterialize()
696 unsigned Phys = VRM.getPhys(VirtReg); in ReMaterialize()
873 VirtRegMap &VRM) { in GetRegForReload() argument
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DAllocationOrder.cpp26 const VirtRegMap &VRM, in AllocationOrder() argument
29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); in AllocationOrder()
31 VRM.getRegInfo().getRegAllocationHint(VirtReg); in AllocationOrder()
38 Hint = VRM.getPhys(Hint); in AllocationOrder()
42 const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); in AllocationOrder()
46 VRM.getMachineFunction()); in AllocationOrder()
61 VRM.getMachineFunction()); in AllocationOrder()
DRegAllocBasic.cpp204 if (!VRM->hasPhys(reg)) continue; // spilled? in verify()
205 unsigned PhysReg = VRM->getPhys(reg); in verify()
234 VRM = &vrm; in init()
279 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
280 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
289 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign"); in unassign()
291 VRM->clearVirt(VirtReg.reg); in unassign()
302 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
338 VRM->assignVirt2Phys(VirtReg->reg, in allocatePhysRegs()
349 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
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DLiveRangeEdit.cpp34 VirtRegMap &VRM) { in createFrom() argument
35 MachineRegisterInfo &MRI = VRM.getRegInfo(); in createFrom()
37 VRM.grow(); in createFrom()
38 VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg)); in createFrom()
212 LiveIntervals &LIS, VirtRegMap &VRM, in eliminateDeadDefs() argument
217 MachineRegisterInfo &MRI = VRM.getRegInfo(); in eliminateDeadDefs()
301 bool IsOriginal = VRM.getOriginal(LI->reg) == LI->reg; in eliminateDeadDefs()
305 Dups.push_back(&createFrom(LI->reg, LIS, VRM)); in eliminateDeadDefs()
310 VRM.setIsSplitFromReg(Dups.back()->reg, 0); in eliminateDeadDefs()
DLiveDebugVariables.cpp260 void rewriteLocations(VirtRegMap &VRM, const TargetRegisterInfo &TRI);
263 void emitDebugValues(VirtRegMap *VRM,
344 void emitDebugValues(VirtRegMap *VRM);
876 UserValue::rewriteLocations(VirtRegMap &VRM, const TargetRegisterInfo &TRI) { in rewriteLocations() argument
886 if (VRM.isAssignedReg(VirtReg) && in rewriteLocations()
887 TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) { in rewriteLocations()
891 Loc.substPhysReg(VRM.getPhys(VirtReg), TRI); in rewriteLocations()
892 } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT && in rewriteLocations()
893 VRM.isSpillSlotUsed(VRM.getStackSlot(VirtReg))) { in rewriteLocations()
895 Loc = MachineOperand::CreateFI(VRM.getStackSlot(VirtReg)); in rewriteLocations()
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DInlineSpiller.cpp61 VirtRegMap &VRM; member in __anonac620b3c0111::InlineSpiller
146 VRM(vrm), in InlineSpiller()
311 VRM.getOriginal(Reg) == Original; in isSibling()
729 VRM.addSpillSlotUse(StackSlot, MII); in hoistSpill()
890 LiveInterval &NewLI = Edit->createFrom(Original, LIS, VRM); in reMaterializeFor()
961 Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII); in reMaterializeAll()
1046 VRM.addSpillSlotUse(StackSlot, FoldMI); in foldMemoryOperand()
1067 VRM.addSpillSlotUse(StackSlot, MI); in insertReload()
1083 VRM.addSpillSlotUse(StackSlot, MI); in insertSpill()
1168 LiveInterval &NewLI = Edit->createFrom(Reg, LIS, VRM); in spillAroundUses()
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DRegAllocBase.h93 VirtRegMap *VRM; variable
102 RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {} in RegAllocBase()
DRegAllocGreedy.cpp355 VRM->RemoveMachineInstrFromMaps(MI); in LRE_WillEraseInstruction()
359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { in LRE_CanEraseVirtReg()
369 unsigned PhysReg = VRM->getPhys(VirtReg); in LRE_WillShrinkVirtReg()
423 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg))) in enqueue()
563 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg); in canEvictInterference()
598 unassign(*Intf, VRM->getPhys(Intf->reg)); in evictInterference()
1557 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); in selectOrSplit()
1620 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); in runOnMachineFunction()
1626 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops)); in runOnMachineFunction()
1627 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree)); in runOnMachineFunction()
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DStackSlotColoring.cpp61 VirtRegMap* VRM; member in __anon2bd015f70111::StackSlotColoring
257 if (!(ColorWithRegs || ColorWithRegsOpt) || !VRM->HasUnusedRegisters()) in ColorSlotsWithFreeRegs()
282 unsigned Reg = VRM->getFirstUnusedRegister(RC); in ColorSlotsWithFreeRegs()
304 VRM->setRegisterUsed(Reg); in ColorSlotsWithFreeRegs()
309 VRM->setRegisterUsed(*AS); in ColorSlotsWithFreeRegs()
725 VRM = &getAnalysis<VirtRegMap>(); in runOnMachineFunction()
732 if (NumSlots == 0 || !VRM->HasUnusedRegisters()) in runOnMachineFunction()
DLiveRangeEdit.h133 LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) { in create() argument
134 return createFrom(getReg(), LIS, VRM); in create()
DSplitKit.cpp46 VRM(vrm), in SplitAnalysis()
277 unsigned OrigReg = VRM.getOriginal(CurLI->reg); in isOriginalEndpoint()
306 : SA(sa), LIS(lis), VRM(vrm), in SplitEditor()
325 LRCalc[0].reset(&VRM.getMachineFunction()); in reset()
327 LRCalc[1].reset(&VRM.getMachineFunction()); in reset()
438 Edit->create(LIS, VRM); in openIntv()
442 Edit->create(LIS, VRM); in openIntv()
1015 Edit->eliminateDeadDefs(Dead, LIS, VRM, TII); in deleteRematVictims()
1092 dups.push_back(&Edit->create(LIS, VRM)); in finish()
1100 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops); in finish()
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/external/llvm/lib/CodeGen/
DLiveRangeEdit.cpp36 if (VRM) { in createEmptyIntervalFrom()
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createEmptyIntervalFrom()
45 if (VRM) { in createFrom()
46 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom()
66 unsigned Original = VRM->getOriginal(getReg()); in scanRemattable()
266 if (VRM && MI->getOperand(0).isReg()) { in eliminateDeadDef()
268 unsigned Original = VRM->getOriginal(Dest); in eliminateDeadDef()
410 unsigned Original = VRM ? VRM->getOriginal(VReg) : 0; in eliminateDeadDefs()
416 VRM->setIsSplitFromReg(SplitLI->reg, Original); in eliminateDeadDefs()
428 if (VRM) in MRI_NoteNewVirtualRegister()
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DCalcSpillWeights.cpp28 VirtRegMap *VRM, in calculateSpillWeightsAndHints() argument
36 VirtRegAuxInfo VRAI(MF, LIS, VRM, MLI, MBFI, norm); in calculateSpillWeightsAndHints()
79 VirtRegMap *VRM, in isRematerializable() argument
82 unsigned Original = VRM ? VRM->getOriginal(Reg) : 0; in isRematerializable()
97 if (VRM) { in isRematerializable()
109 VRM->getOriginal(Reg) != Original) in isRematerializable()
232 if (isRematerializable(li, LIS, VRM, *MF.getSubtarget().getInstrInfo())) in calculateSpillWeightAndHint()
DAllocationOrder.cpp31 const VirtRegMap &VRM, in AllocationOrder() argument
35 const MachineFunction &MF = VRM.getMachineFunction(); in AllocationOrder()
36 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); in AllocationOrder()
38 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in AllocationOrder()
DRegAllocBasic.cpp194 if (!VRM->hasPhys(Spill.reg)) in spillInterferences()
202 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats); in spillInterferences()
226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit()
261 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats); in selectOrSplit()
279 calculateSpillWeightsAndHints(*LIS, *MF, VRM, in runOnMachineFunction()
283 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); in runOnMachineFunction()
289 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n"); in runOnMachineFunction()
DRegAllocPBQP.cpp136 void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
140 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
147 VirtRegMap &VRM,
153 VirtRegMap &VRM) const;
561 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, in initializeGraph() argument
614 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller); in initializeGraph()
638 VirtRegMap &VRM, Spiller &VRegSpiller) { in spillVReg() argument
641 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM, in spillVReg()
665 VirtRegMap &VRM, in mapPBQPToRegAlloc() argument
676 VRM.clearAllVirt(); in mapPBQPToRegAlloc()
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DLiveRegMatrix.cpp52 VRM = &getAnalysis<VirtRegMap>(); in runOnMachineFunction()
100 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign()
118 VRM->clearVirt(VirtReg.reg); in unassign()
DRegAllocBase.cpp59 VRM = &vrm; in init()
86 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
127 VRM->assignVirt2Phys(VirtReg->reg, in allocatePhysRegs()
138 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
DVirtRegMap.cpp163 VirtRegMap *VRM; member in __anon1700c3f70111::VirtRegRewriter
219 VRM = &getAnalysis<VirtRegMap>(); in runOnMachineFunction()
223 DEBUG(VRM->dump()); in runOnMachineFunction()
226 LIS->addKillFlags(VRM); in runOnMachineFunction()
235 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM); in runOnMachineFunction()
239 VRM->clearAllVirt(); in runOnMachineFunction()
299 unsigned PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns()
399 unsigned PhysReg = VRM->getPhys(VirtReg); in rewrite()
DLiveDebugVariables.cpp267 void rewriteLocations(VirtRegMap &VRM, const TargetRegisterInfo &TRI);
270 void emitDebugValues(VirtRegMap *VRM,
355 void emitDebugValues(VirtRegMap *VRM);
914 UserValue::rewriteLocations(VirtRegMap &VRM, const TargetRegisterInfo &TRI) { in rewriteLocations() argument
924 if (VRM.isAssignedReg(VirtReg) && in rewriteLocations()
925 TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) { in rewriteLocations()
929 Loc.substPhysReg(VRM.getPhys(VirtReg), TRI); in rewriteLocations()
930 } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) { in rewriteLocations()
932 Loc = MachineOperand::CreateFI(VRM.getStackSlot(VirtReg)); in rewriteLocations()
987 void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, in emitDebugValues() argument
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DInlineSpiller.cpp66 VirtRegMap &VRM; member in __anonf7bb34900111::HoistSpillHelper
116 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm), in HoistSpillHelper()
137 VirtRegMap &VRM; member in __anonf7bb34900111::InlineSpiller
174 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm), in InlineSpiller()
328 VRM.getOriginal(Reg) == Original; in isSibling()
977 StackSlot = VRM.assignVirt2StackSlot(Original); in spillAll()
984 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot); in spillAll()
1026 Original = VRM.getOriginal(edit.getReg()); in spill()
1027 StackSlot = VRM.getStackSlot(Original); in spill()
1367 LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this); in hoistAllSpills()
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DRegAllocBase.h63 VirtRegMap *VRM; variable
75 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {} in RegAllocBase()
DRegAllocGreedy.cpp495 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg()
507 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
594 if (VRM->hasKnownPreference(Reg)) in enqueue()
663 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in canReassign()
779 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg); in canEvictInterference()
832 if (!VRM->hasPhys(Intf->reg)) in evictInterference()
1470 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in doRegionSplit()
1518 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryBlockSplit()
1590 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryInstructionSplit()
1913 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryLocalSplit()
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/external/llvm/include/llvm/CodeGen/
DCalcSpillWeights.h55 VirtRegMap *VRM; variable
66 : MF(mf), LIS(lis), VRM(vrm), Loops(loops), MBFI(mbfi), normalize(norm) {} in MF()
75 VirtRegMap *VRM,
DVirtRegMap.h184 inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
185 VRM.print(OS);

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