/external/mesa3d/src/mesa/x86/ |
D | sse_xform3.S | 85 MOVSS ( REGOFF(0, ESI), XMM4 ) /* | | | ox */ 86 SHUFPS ( CONST(0x0), XMM4, XMM4 ) /* ox | ox | ox | ox */ 92 MULPS ( XMM0, XMM4 ) /* m3*ox | m2*ox | m1*ox | m0*ox */ 96 ADDPS ( XMM5, XMM4 ) 97 ADDPS ( XMM6, XMM4 ) 98 ADDPS ( XMM3, XMM4 ) 100 MOVAPS ( XMM4, REGOFF(0, EDI) ) 209 MOVSS ( M(14), XMM4 ) /* - | - | - | m14 */ 221 ADDSS ( XMM4, XMM0 ) /* +m14 */ 274 MOVSS ( M(14), XMM4 ) /* m14 */ [all …]
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D | sse_normal.S | 142 MOVSS ( ARG_SCALE, XMM4 ) /* scale */ 143 SHUFPS ( CONST(0x0), XMM4, XMM4 ) /* scale | scale */ 145 MULPS ( XMM4, XMM0 ) /* m4*scale | m0*scale */ 149 MULPS ( XMM4, XMM1 ) /* m5*scale | m1*scale */ 153 MULPS ( XMM4, XMM2 ) /* m6*scale | m2*scale */ 165 MOVSS ( S(1), XMM4 ) /* uy */ 166 SHUFPS ( CONST(0x0), XMM4, XMM4 ) /* uy | uy */ 167 MULPS ( XMM1, XMM4 ) /* uy*m5 | uy*m1 */ 172 ADDPS ( XMM4, XMM3 ) 179 MOVSS ( S(1), XMM4 ) /* uy */ [all …]
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D | sse_xform4.S | 70 MOVAPS( MAT(0), XMM4 ) /* m3 | m2 | m1 | m0 */ 80 MULPS( XMM4, XMM0 ) /* ox*m3 | ox*m2 | ox*m1 | ox*m0 */ 150 MOVSS( SRC(0), XMM4 ) /* ox */ 151 SHUFPS( CONST(0x0), XMM4, XMM4 ) /* ox | ox | ox | ox */ 152 MULPS( XMM0, XMM4 ) /* ox*m3 | ox*m2 | ox*m1 | ox*m0 */ 166 ADDPS( XMM5, XMM4 ) /* ox*m3+oy*m7 | ... */ 167 ADDPS( XMM6, XMM4 ) /* ox*m3+oy*m7+oz*m11 | ... */ 168 ADDPS( XMM7, XMM4 ) /* ox*m3+oy*m7+oz*m11+ow*m15 | ... */ 169 MOVAPS( XMM4, DST(0) ) /* ->D(3) | ->D(2) | ->D(1) | ->D(0) */ 171 MOVSS( SRC(3), XMM4 ) /* ow */ [all …]
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D | sse_xform2.S | 85 MOVSS( S(1), XMM4 ) /* oy */ 86 SHUFPS( CONST(0x0), XMM4, XMM4 ) /* oy | oy | oy | oy */ 87 MULPS( XMM1, XMM4 ) /* oy*m7 | oy*m6 | oy*m5 | oy*m4 */ 89 ADDPS( XMM4, XMM3 ) 259 MOVLPS( S(0), XMM4 ) /* oy | ox */ 260 MULPS( XMM1, XMM4 ) /* oy*m5 | ox*m0 */ 261 MOVLPS( XMM4, D(0) ) /* ->D(1) | ->D(0) */ 320 MOVSS( S(1), XMM4 ) /* oy */ 321 SHUFPS( CONST(0x0), XMM4, XMM4 ) /* oy | oy */ 322 MULPS( XMM1, XMM4 ) /* oy*m5 | oy*m4 */ [all …]
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D | sse_xform1.S | 193 MOVSS( S(0), XMM4 ) /* ox */ 194 MULSS( XMM0, XMM4 ) /* ox*m0 */ 195 ADDSS( XMM1, XMM4 ) /* ox*m0+m12 */ 196 MOVSS( XMM4, D(0) )
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/external/swiftshader/third_party/LLVM/test/TableGen/ |
D | Slice.td | 45 def XMM4: Register<"xmm4">; 59 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | cast.td | 45 def XMM4: Register<"xmm4">; 59 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | TargetInstrSpec.td | 46 def XMM4: Register<"xmm4">; 60 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | MultiPat.td | 54 def XMM4: Register<"xmm4">; 68 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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/external/llvm/test/TableGen/ |
D | Slice.td | 44 def XMM4: Register<"xmm4">; 58 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | TargetInstrSpec.td | 51 def XMM4: Register<"xmm4">; 65 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | cast.td | 50 def XMM4: Register<"xmm4">; 64 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | MultiPat.td | 54 def XMM4: Register<"xmm4">; 68 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86InstrControl.td | 143 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 182 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 218 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 250 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS], 283 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
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D | X86GenRegisterInfo.inc | 151 XMM4 = 132, 380 const unsigned XMM4_Overlaps[] = { X86::XMM4, X86::YMM4, 0 }; 396 const unsigned YMM4_Overlaps[] = { X86::YMM4, X86::XMM4, 0 }; 479 const unsigned YMM4_SubRegsSet[] = { X86::XMM4, 0 }; 697 { "XMM4", XMM4_Overlaps, XMM4_SubRegsSet, XMM4_SuperRegsSet }, 770 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 790 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 810 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 1218 RI->mapDwarfRegToLLVMReg(21, X86::XMM4, false ); 1261 RI->mapDwarfRegToLLVMReg(25, X86::XMM4, false ); [all …]
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D | X86RegisterInfo.td | 172 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>; 195 def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias<XMM4>;
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D | X86CallingConv.td | 159 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 237 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
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D | X86GenCallingConv.inc | 548 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 653 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
D | ghc-cc64.ll | 19 @f4 = external global float ; assigned to register: XMM4
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/external/llvm/test/CodeGen/X86/ |
D | ghc-cc64.ll | 19 @f4 = external global float ; assigned to register: XMM4
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/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 211 ENTRY(XMM4) \
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/external/llvm/lib/Target/X86/ |
D | X86CallingConv.td | 333 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 442 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>, 468 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>> 664 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>,
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/external/llvm/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 221 ENTRY(XMM4) \
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
D | X86MCTargetDesc.cpp | 187 case X86::XMM4: case X86::XMM12: in getX86RegNum()
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/external/valgrind/memcheck/ |
D | mc_machine.c | 718 if (o >= GOF(XMM4) && o+sz <= GOF(XMM4)+SZB(XMM4)) return GOF(XMM4); in get_otrack_shadow_offset_wrk()
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