/external/mesa3d/src/mesa/x86/ |
D | sse_xform3.S | 87 MOVSS ( REGOFF(4, ESI), XMM5 ) /* | | | oy */ 88 SHUFPS ( CONST(0x0), XMM5, XMM5 ) /* oy | oy | oy | oy */ 93 MULPS ( XMM1, XMM5 ) /* m7*oy | m6*oy | m5*oy | m4*oy */ 96 ADDPS ( XMM5, XMM4 ) 281 MOVSS ( S(2), XMM5 ) /* oz */ 282 SHUFPS ( CONST(0x0), XMM5, XMM5 ) /* oz | oz */ 283 MULPS ( XMM2, XMM5 ) /* oz*m9 | oz*m8 */ 284 ADDPS ( XMM5, XMM0 ) /* +oy*m5 | +ox*m0 */ 293 MOVSS ( XMM6, XMM5 ) /* 0 */ 294 SUBPS ( XMM0, XMM5 ) /* -oz */ [all …]
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D | sse_normal.S | 168 MOVSS ( S(2), XMM5 ) /* uz */ 169 SHUFPS ( CONST(0x0), XMM5, XMM5 ) /* uz | uz */ 170 MULPS ( XMM2, XMM5 ) /* uz*m6 | uz*m2 */ 173 ADDPS ( XMM5, XMM3 ) 181 MOVSS ( S(0), XMM5 ) /* ux */ 182 MULSS ( XMM6, XMM5 ) /* ux*m8*scale */ 185 ADDSS ( XMM5, XMM3 )
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D | sse_xform4.S | 71 MOVAPS( MAT(4), XMM5 ) /* m7 | m6 | m5 | m4 */ 84 MULPS( XMM5, XMM1 ) /* oy*m7 | oy*m6 | oy*m5 | oy*m4 */ 154 MOVSS( SRC(1), XMM5 ) /* oy */ 155 SHUFPS( CONST(0x0), XMM5, XMM5 ) /* oy | oy | oy | oy */ 156 MULPS( XMM1, XMM5 ) /* oy*m7 | oy*m6 | oy*m5 | oy*m4 */ 166 ADDPS( XMM5, XMM4 ) /* ox*m3+oy*m7 | ... */
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/external/swiftshader/third_party/LLVM/test/TableGen/ |
D | Slice.td | 46 def XMM5: Register<"xmm5">; 59 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | cast.td | 46 def XMM5: Register<"xmm5">; 59 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | TargetInstrSpec.td | 47 def XMM5: Register<"xmm5">; 60 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | MultiPat.td | 55 def XMM5: Register<"xmm5">; 68 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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/external/llvm/test/TableGen/ |
D | Slice.td | 45 def XMM5: Register<"xmm5">; 58 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | TargetInstrSpec.td | 52 def XMM5: Register<"xmm5">; 65 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | cast.td | 51 def XMM5: Register<"xmm5">; 64 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | MultiPat.td | 55 def XMM5: Register<"xmm5">; 68 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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/external/llvm/test/MC/X86/ |
D | intel-syntax-encoding.s | 59 movsd XMM5, QWORD PTR [-8]
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D | intel-syntax.s | 79 movsd XMM5, QWORD PTR [-8]
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86InstrControl.td | 143 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 182 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 218 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 250 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS], 283 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
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D | X86GenRegisterInfo.inc | 152 XMM5 = 133, 381 const unsigned XMM5_Overlaps[] = { X86::XMM5, X86::YMM5, 0 }; 397 const unsigned YMM5_Overlaps[] = { X86::YMM5, X86::XMM5, 0 }; 480 const unsigned YMM5_SubRegsSet[] = { X86::XMM5, 0 }; 698 { "XMM5", XMM5_Overlaps, XMM5_SubRegsSet, XMM5_SuperRegsSet }, 770 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 790 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 810 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 1219 RI->mapDwarfRegToLLVMReg(22, X86::XMM5, false ); 1262 RI->mapDwarfRegToLLVMReg(26, X86::XMM5, false ); [all …]
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D | X86RegisterInfo.td | 173 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>; 196 def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias<XMM5>;
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D | X86CallingConv.td | 159 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 237 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
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D | X86GenCallingConv.inc | 548 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 653 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
D | ghc-cc64.ll | 20 @d1 = external global double ; assigned to register: XMM5
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/external/llvm/test/CodeGen/X86/ |
D | ghc-cc64.ll | 20 @d1 = external global double ; assigned to register: XMM5
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/external/llvm/lib/Target/X86/ |
D | X86CallingConv.td | 333 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 440 // XMM0-XMM5. 442 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>, 468 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>> 662 // XMM0-XMM5. 664 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>,
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/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 212 ENTRY(XMM5) \
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/external/llvm/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 222 ENTRY(XMM5) \
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
D | X86MCTargetDesc.cpp | 190 case X86::XMM5: case X86::XMM13: in getX86RegNum()
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/external/valgrind/memcheck/ |
D | mc_machine.c | 719 if (o >= GOF(XMM5) && o+sz <= GOF(XMM5)+SZB(XMM5)) return GOF(XMM5); in get_otrack_shadow_offset_wrk()
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