/external/mesa3d/src/mesa/x86/ |
D | sse_xform4.S | 73 MOVAPS( MAT(12), XMM7 ) /* m15 | m14 | m13 | m12 */ 92 MULPS( XMM7, XMM3 ) /* ow*m15 | ow*m14 | ow*m13 | ow*m12 */ 162 MOVSS( SRC(3), XMM7 ) /* ow */ 163 SHUFPS( CONST(0x0), XMM7, XMM7 ) /* ow | ow | ow | ow */ 164 MULPS( XMM3, XMM7 ) /* ow*m15 | ow*m14 | ow*m13 | ow*m12 */ 168 ADDPS( XMM7, XMM4 ) /* ox*m3+oy*m7+oz*m11+ow*m15 | ... */
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D | sse_normal.S | 157 MOVSS ( M(9), XMM7 ) /* m9 */ 158 MULSS ( ARG_SCALE, XMM7 ) /* m9*scale */ 180 MULSS ( XMM7, XMM4 ) /* uy*m9*scale */
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/external/swiftshader/third_party/LLVM/test/TableGen/ |
D | Slice.td | 48 def XMM7: Register<"xmm7">; 59 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | cast.td | 48 def XMM7: Register<"xmm7">; 59 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | TargetInstrSpec.td | 49 def XMM7: Register<"xmm7">; 60 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | MultiPat.td | 57 def XMM7: Register<"xmm7">; 68 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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/external/llvm/test/TableGen/ |
D | Slice.td | 47 def XMM7: Register<"xmm7">; 58 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | TargetInstrSpec.td | 54 def XMM7: Register<"xmm7">; 65 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | cast.td | 53 def XMM7: Register<"xmm7">; 64 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | MultiPat.td | 57 def XMM7: Register<"xmm7">; 68 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86GenRegisterInfo.inc | 154 XMM7 = 135, 383 const unsigned XMM7_Overlaps[] = { X86::XMM7, X86::YMM7, 0 }; 399 const unsigned YMM7_Overlaps[] = { X86::YMM7, X86::XMM7, 0 }; 482 const unsigned YMM7_SubRegsSet[] = { X86::XMM7, 0 }; 700 { "XMM7", XMM7_Overlaps, XMM7_SubRegsSet, XMM7_SuperRegsSet }, 770 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 790 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 810 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,… 1221 RI->mapDwarfRegToLLVMReg(24, X86::XMM7, false ); 1264 RI->mapDwarfRegToLLVMReg(28, X86::XMM7, false ); [all …]
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D | X86InstrControl.td | 143 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 182 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 218 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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D | X86RegisterInfo.td | 175 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>; 198 def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias<XMM7>;
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D | X86CallingConv.td | 159 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
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D | X86RegisterInfo.cpp | 372 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, in getCalleeSavedRegs()
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D | X86GenCallingConv.inc | 548 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
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/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 214 ENTRY(XMM7) \
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/external/llvm/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 224 ENTRY(XMM7) \
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
D | X86MCTargetDesc.cpp | 196 case X86::XMM7: case X86::XMM15: in getX86RegNum()
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/external/valgrind/memcheck/ |
D | mc_machine.c | 721 if (o >= GOF(XMM7) && o+sz <= GOF(XMM7)+SZB(XMM7)) return GOF(XMM7); in get_otrack_shadow_offset_wrk()
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/external/llvm/docs/TableGen/ |
D | index.rst | 70 XMM6, XMM7, XMM8, XMM9,
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D | LangIntro.rst | 544 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
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/external/libvpx/libvpx/third_party/x86inc/ |
D | x86inc.asm | 540 ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.
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/external/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 179 def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
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D | X86FastISel.cpp | 2958 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 in fastLowerArguments() 3271 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 in fastLowerCall()
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