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Searched refs:ZEROReg (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td875 multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {
877 (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
879 (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
881 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
893 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
DMipsSEInstrInfo.cpp475 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in loadImmediate() local
494 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) in loadImmediate()
DMipsInstrInfo.td2563 Instruction SLTiuOp, Register ZEROReg> {
2565 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
2567 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
2588 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
2600 Instruction SLTuOp, Register ZEROReg> {
2604 (SLTuOp ZEROReg, RC:$lhs)>;
2608 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrInfo.td927 Instruction SLTiuOp, Register ZEROReg> {
929 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
931 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
948 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
987 Instruction SLTuOp, Register ZEROReg> {
991 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;