| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| D | valid-xfail-mips32r6.txt | 10 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 256
11 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 256
12 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256
|
| D | valid-mips32r6-el.txt | 20 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
|
| D | valid-mips32r6.txt | 59 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| D | valid-xfail-mips64r6.txt | 10 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 260
11 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 260
12 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
|
| D | valid-mips64r6-el.txt | 20 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
|
| D | valid-mips64r6.txt | 76 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
|
| /external/llvm/test/CodeGen/Mips/compactbranches/ |
| D | no-beqzc-bnezc.ll | 37 ; beqc and bnec have the restriction that $rs < $rt.
41 ; ENCODING-NOT: beqc $5, $4
|
| D | beqc-bnec-register-constraint.ll | 3 ; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
36 ; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
|
| D | compact-branches.ll | 41 ; CHECK beqc
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | relocations.s | 11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
61 beqc $5, $6, bar
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | relocations.s | 11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
66 beqc $5, $6, bar
|
| /external/v8/src/mips/ |
| D | assembler-mips.h | 673 void beqc(Register rs, Register rt, int16_t offset);
674 inline void beqc(Register rs, Register rt, Label* L) { in beqc() function
675 beqc(rs, rt, shifted_branch_offset(L)); in beqc()
|
| D | assembler-mips.cc | 1483 void Assembler::beqc(Register rs, Register rt, int16_t offset) { in beqc() function in v8::internal::Assembler
|
| D | macro-assembler-mips.cc | 2888 beqc(rs, scratch, offset); in BranchShortHelperR6()
|
| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 680 void beqc(Register rs, Register rt, int16_t offset);
681 inline void beqc(Register rs, Register rt, Label* L) { in beqc() function
682 beqc(rs, rt, shifted_branch_offset(L)); in beqc()
|
| D | assembler-mips64.cc | 1469 void Assembler::beqc(Register rs, Register rt, int16_t offset) { in beqc() function in v8::internal::Assembler
|
| D | macro-assembler-mips64.cc | 3074 beqc(rs, scratch, offset); in BranchShortHelperR6()
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 23 beqc $3,$4, 16 # CHECK: beqc $3, $4, 16 # encoding: [0x74,0x83,0x00,0x08]
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 42 0x74 0x83 0x00 0x08 # CHECK: beqc $3, $4, 16
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 65 class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
288 class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_mm,
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| D | Mips32r6InstrInfo.td | 397 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
|