| /external/llvm/test/CodeGen/Mips/compactbranches/ |
| D | no-beqzc-bnezc.ll | 5 ; bnezc and beqzc have restriction that $rt != 0
9 ; CHECK-NOT: bnezc $0
|
| D | beqc-bnec-register-constraint.ll | 4 ; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc.
|
| D | compact-branches.ll | 148 ; CHECK: bnezc
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | relocations.s | 23 # CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
43 bnezc $3, bar
|
| D | valid.s | 36 bnezc $3, 64 # CHECK: bnezc $3, 64 # encoding: [0xa0,0x60,0x00,0x20]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | relocations.s | 26 # CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
48 bnezc $3, bar
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fpbr.ll | 22 ; 64-GPR: bnezc $[[GPRCC]], $BB0_2
56 ; 64-GPR: bnezc $[[GPRCC]], $BB1_2
117 ; 64-GPR: bnezc $[[GPRCC]], $BB3_2
147 ; 64-GPR: bnezc $[[GPRCC]], $BB4_2
|
| D | micromips-compact-branches.ll | 19 ; CHECK: bnezc
|
| D | analyzebranch.ll | 22 ; GPR: bnezc $[[GPRCC]], $BB
|
| D | fcmp.ll | 1076 ; 32-CMP-DAG: bnezc $[[T4]],
1089 ; 64-CMP-DAG: bnezc $[[T4]],
1145 ; 32-CMP-DAG: bnezc $[[T4]],
1158 ; 64-CMP-DAG: bnezc $[[T4]],
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | relocations.s | 20 # CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
64 bnezc $9, bar
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | relocations.s | 20 # CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
69 bnezc $9, bar
|
| /external/llvm/test/ExecutionEngine/RuntimeDyld/Mips/ |
| D | ELF_N64R6_relocations.s | 37 bnezc $5,foo
|
| D | ELF_O32R6_relocations.s | 32 bnezc $5,foo
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| D | valid-mips64r6-el.txt | 52 0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72260
53 0xfa 0xff 0x5f 0xf8 # CHECK: bnezc $2, -20
|
| D | valid-mips64r6.txt | 215 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
216 0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| D | valid-mips32r6.txt | 190 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
191 0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20
|
| D | valid-mips32r6-el.txt | 32 0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72260
|
| /external/v8/src/mips/ |
| D | assembler-mips.h | 689 void bnezc(Register rt, int32_t offset);
690 inline void bnezc(Register rt, Label* L) { in bnezc() function
691 bnezc(rt, shifted_branch_offset21(L)); in bnezc()
|
| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 696 void bnezc(Register rt, int32_t offset);
697 inline void bnezc(Register rt, Label* L) { in bnezc() function
698 bnezc(rt, shifted_branch_offset21(L)); in bnezc()
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid.txt | 159 0x40 0xa9 0x02 0x9a # CHECK: bnezc $9, 1332
|
| D | valid-el.txt | 159 0xa9 0x40 0x9a 0x02 # CHECK: bnezc $9, 1332
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 58 class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
1252 : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1253 MMR6Arch<"bnezc">;
|
| D | MipsSchedule.td | 52 def II_BCCZC : InstrItinClass; // beqzc, bnezc
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 55 0xa0 0x60 0x00 0x20 # CHECK: bnezc $3, 64
|