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Searched refs:buffer_store_dwordx4 (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dload-constant-i32.ll185 ; GCN-NOHSA-DAG: buffer_store_dwordx4
186 ; GCN-NOHSA-DAG: buffer_store_dwordx4
187 ; GCN-NOHSA-DAG: buffer_store_dwordx4
188 ; GCN-NOHSA-DAG: buffer_store_dwordx4
213 ; GCN-NOHSA-DAG: buffer_store_dwordx4
214 ; GCN-NOHSA-DAG: buffer_store_dwordx4
215 ; GCN-NOHSA-DAG: buffer_store_dwordx4
216 ; GCN-NOHSA-DAG: buffer_store_dwordx4
253 ; GCN-NOHSA: buffer_store_dwordx4
254 ; GCN-NOHSA: buffer_store_dwordx4
[all …]
Dload-global-i32.ll155 ; GCN-NOHSA: buffer_store_dwordx4
173 ; GCN-NOHSA-DAG: buffer_store_dwordx4
184 ; GCN-NOHSA: buffer_store_dwordx4
185 ; GCN-NOHSA: buffer_store_dwordx4
206 ; GCN-NOHSA-DAG: buffer_store_dwordx4
207 ; GCN-NOHSA-DAG: buffer_store_dwordx4
225 ; GCN-NOHSA-DAG: buffer_store_dwordx4
226 ; GCN-NOHSA-DAG: buffer_store_dwordx4
227 ; GCN-NOHSA-DAG: buffer_store_dwordx4
228 ; GCN-NOHSA-DAG: buffer_store_dwordx4
[all …]
Dinsert_vector_elt.ll20 ; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]:
109 ; GCN: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]:
118 ; GCN: buffer_store_dwordx4
119 ; GCN: buffer_store_dwordx4
128 ; GCN: buffer_store_dwordx4
129 ; GCN: buffer_store_dwordx4
130 ; GCN: buffer_store_dwordx4
131 ; GCN: buffer_store_dwordx4
160 ; GCN: buffer_store_dwordx4
169 ; GCN: buffer_store_dwordx4
[all …]
Dllvm.amdgcn.buffer.store.ll5 ;CHECK: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
6 ;CHECK: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 glc
7 ;CHECK: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 slc
17 ;CHECK: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:42
25 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
33 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen
41 ;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
50 ;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
60 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
64 ;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
Dreorder-stores.ll7 ; SI: buffer_store_dwordx4
8 ; SI: buffer_store_dwordx4
37 ; SI: buffer_store_dwordx4
38 ; SI: buffer_store_dwordx4
39 ; SI: buffer_store_dwordx4
40 ; SI: buffer_store_dwordx4
Dds_read2_superreg.ll89 ; CI: buffer_store_dwordx4 [[REG_ZW]]
102 ; CI: buffer_store_dwordx4 [[REG_ZW]]
117 ; CI-DAG: buffer_store_dwordx4 [[VEC_HI]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 off…
118 ; CI-DAG: buffer_store_dwordx4 [[VEC_LO]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64{{$}}
136 ; CI-DAG: buffer_store_dwordx4 [[VEC0_3]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64{{$}}
137 ; CI-DAG: buffer_store_dwordx4 [[VEC4_7]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 off…
138 ; CI-DAG: buffer_store_dwordx4 [[VEC8_11]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 of…
139 ; CI-DAG: buffer_store_dwordx4 [[VEC12_15]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 o…
177 ; CI: buffer_store_dwordx4 v{{\[}}[[REG_ELT0]]:[[REG_ELT3]]{{\]}}
Dshift-and-i128-ubfe.ll12 ; GCN: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[…
34 ; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9…
56 ; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9…
78 ; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9…
102 ; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[OR0]]:[[ZERO]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:…
Dtrunc-store.ll5 ; SI: buffer_store_dwordx4
13 ; SI: buffer_store_dwordx4
Dmerge-stores.ll109 ; GCN: buffer_store_dwordx4 v{{\[}}[[LO]]:[[HI]]{{\]}}
123 ; GCN: buffer_store_dwordx4
138 ; GCN: buffer_store_dwordx4
194 ; GCN: buffer_store_dwordx4
204 ; GCN: buffer_store_dwordx4
205 ; GCN: buffer_store_dwordx4
269 ; GCN: buffer_store_dwordx4 [[LOAD]]
315 ; GCN: buffer_store_dwordx4 [[LOAD]]
338 ; GCN: buffer_store_dwordx4 [[LOAD]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28
364 ; GCN: buffer_store_dwordx4 [[LOAD]]
[all …]
Dextract-vector-elt-build-vector-combine.ll9 ; GCN: buffer_store_dwordx4
10 ; GCN: buffer_store_dwordx4
52 ; GCN: buffer_store_dwordx4
98 ; GCN: buffer_store_dwordx4
Dhalf.ll124 ; GCN: buffer_store_dwordx4
125 ; GCN: buffer_store_dwordx4
261 ; GCN: buffer_store_dwordx4 [[TMP:v\[[0-9]+:[0-9]+\]]]
339 ; GCN: buffer_store_dwordx4
340 ; GCN: buffer_store_dwordx4
341 ; GCN: buffer_store_dwordx4
342 ; GCN: buffer_store_dwordx4
371 ; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[CVT2_LO]]:[[CVT3_HI]]{{\]}}
393 ; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
495 ; GCN: buffer_store_dwordx4
[all …]
Dllvm.memcpy.ll293 ; SI: buffer_store_dwordx4
294 ; SI: buffer_store_dwordx4
306 ; SI: buffer_store_dwordx4
307 ; SI: buffer_store_dwordx4
319 ; SI: buffer_store_dwordx4
320 ; SI: buffer_store_dwordx4
Dfadd64.ll26 ; CHECK: buffer_store_dwordx4
39 ; CHECK: buffer_store_dwordx4
Dprivate-element-size.ll13 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
14 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:…
62 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
63 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:…
64 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:…
65 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:…
205 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
206 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:…
Dcube.ll17 ; GCN: buffer_store_dwordx4
37 ; GCN: buffer_store_dwordx4
Dcvt_f32_ubyte.ll51 ; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
75 ; SI: buffer_store_dwordx4
99 ; SI: buffer_store_dwordx4
136 ; SI: buffer_store_dwordx4
137 ; SI: buffer_store_dwordx4
Dselect-vectors.ll51 ; SI: buffer_store_dwordx4
66 ; SI: buffer_store_dwordx4
122 ; SI: buffer_store_dwordx4
137 ; SI: buffer_store_dwordx4
Dstore-v3i32.ll9 ; SI: buffer_store_dwordx4
Dsalu-to-valu.ll156 ; GCN-NOHSA: buffer_store_dwordx4
190 ; GCN-NOHSA: buffer_store_dwordx4
191 ; GCN-NOHSA: buffer_store_dwordx4
224 ; GCN-NOHSA: buffer_store_dwordx4
225 ; GCN-NOHSA: buffer_store_dwordx4
226 ; GCN-NOHSA: buffer_store_dwordx4
227 ; GCN-NOHSA: buffer_store_dwordx4
Dbuild_vector.ll30 ; SI: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}}
Dindirect-private-64.ll36 ; SI-ALLOCA16: buffer_store_dwordx4
93 ; SI-ALLOCA16: buffer_store_dwordx4
Dcttz_zero_undef.ll59 ; SI: buffer_store_dwordx4
Dunaligned-load-store.ll331 ; UNALIGNED: buffer_store_dwordx4
464 ; SI: buffer_store_dwordx4
514 ; SI: buffer_store_dwordx4
/external/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s69 buffer_store_dwordx4 v[1:4], off, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp1 label
Dmubuf.s477 buffer_store_dwordx4 v[1:4], off, s[4:7], s1 label
481 buffer_store_dwordx4 v[1:4], off, ttmp[4:7], ttmp1 label

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