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Searched refs:cr7 (Results 1 – 25 of 32) sorted by relevance

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/external/v8/src/ppc/
Dassembler-ppc.h290 const CRegister cr7 = {7}; variable
624 void bc_short(Condition cond, Label* L, CRegister cr = cr7,
669 void bclr(Condition cond, CRegister cr = cr7, LKBit lk = LeaveLK) {
713 CRegister cr = cr7) {
755 void b(Condition cond, Label* L, CRegister cr = cr7, LKBit lk = LeaveLK) {
773 void bne(Label* L, CRegister cr = cr7, LKBit lk = LeaveLK) {
776 void beq(Label* L, CRegister cr = cr7, LKBit lk = LeaveLK) {
779 void blt(Label* L, CRegister cr = cr7, LKBit lk = LeaveLK) {
782 void bge(Label* L, CRegister cr = cr7, LKBit lk = LeaveLK) {
785 void ble(Label* L, CRegister cr = cr7, LKBit lk = LeaveLK) {
[all …]
Dmacro-assembler-ppc.h128 CRegister cr = cr7);
141 void Ret(Condition cond, CRegister cr = cr7) { bclr(cond, cr); }
574 CRegister cr = cr7);
576 CRegister cr = cr7);
578 CRegister cr = cr7);
580 CRegister cr = cr7);
588 CRegister cr = cr7);
590 CRegister cr = cr7);
854 CRegister cr = cr7);
1089 void Assert(Condition cond, BailoutReason reason, CRegister cr = cr7);
[all …]
/external/v8/src/crankshaft/ppc/
Dlithium-codegen-ppc.h211 Deoptimizer::BailoutType bailout_type, CRegister cr = cr7);
213 DeoptimizeReason deopt_reason, CRegister cr = cr7);
244 void EmitBranch(InstrType instr, Condition condition, CRegister cr = cr7);
246 void EmitTrueBranch(InstrType instr, Condition condition, CRegister cr = cr7);
249 CRegister cr = cr7);
Dlithium-codegen-ppc.cc2067 const uint crZOrNaNBits = (1 << (31 - Assembler::encode_crbit(cr7, CR_EQ)) | in DoShiftI()
2068 1 << (31 - Assembler::encode_crbit(cr7, CR_FU))); in DoShiftI()
2084 __ fcmpu(reg, kDoubleRegZero, cr7); in DoShiftI()
2107 __ fcmpu(dbl_scratch, kDoubleRegZero, cr7); in DoShiftI()
2200 __ fcmpu(dbl_scratch, kDoubleRegZero, cr7); in DoShiftI()
/external/llvm/test/CodeGen/PowerPC/
Dcc.ll11 …ideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a)
44 …sideeffect "sc", "={r0},={r3},{r0},~{cc},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a)
Daddisdtprelha-nonr3.mir63 …cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
67 …cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
/external/v8/src/regexp/s390/
Dregexp-macro-assembler-s390.h166 void BranchOrBacktrack(Condition condition, Label* to, CRegister cr = cr7);
170 inline void SafeCall(Label* to, Condition cond = al, CRegister cr = cr7);
/external/v8/src/regexp/ppc/
Dregexp-macro-assembler-ppc.h166 void BranchOrBacktrack(Condition condition, Label* to, CRegister cr = cr7);
170 inline void SafeCall(Label* to, Condition cond = al, CRegister cr = cr7);
/external/llvm/test/MC/PowerPC/
Dppc64-regs.s84 #CHECK: .cfi_offset cr7, 627
200 .cfi_offset cr7,627
Dppc64-encoding-ext.s30 beqlr cr7
139 btlr 4*cr7+lt
142 btlr 4*cr7+gt
145 btlr 4*cr7+eq
148 btlr 4*cr7+so
151 btlr 4*cr7+un
/external/v8/src/crankshaft/s390/
Dlithium-codegen-s390.h211 Deoptimizer::BailoutType bailout_type, CRegister cr = cr7);
213 DeoptimizeReason deopt_reason, CRegister cr = cr7);
/external/valgrind/VEX/orig_ppc32/
Ddate.orig330 0x25471B00: 2F800000 cmpi cr7,r0,0
600 0x25471E44: 2B9A000B cmpli cr7,r26,11
666 0x25471B7C: 2F890000 cmpi cr7,r9,0
838 0x25471BDC: 2F890000 cmpi cr7,r9,0
1092 0x25480858: 2F800000 cmpi cr7,r0,0
1572 0x25480AF8: 7F895840 cmpl cr7,r9,r11
1616 0x25480AF8: 7F895840 cmpl cr7,r9,r11
1915 0x25471CB8: 2F8A0000 cmpi cr7,r10,0
2039 0x25471D04: 7F8BF840 cmpl cr7,r11,r31
2081 0x25471D1C: 7F8BF840 cmpl cr7,r11,r31
[all …]
Dreturn0.orig330 0x25471B00: 2F800000 cmpi cr7,r0,0
600 0x25471E44: 2B9A000B cmpli cr7,r26,11
666 0x25471B7C: 2F890000 cmpi cr7,r9,0
838 0x25471BDC: 2F890000 cmpi cr7,r9,0
1092 0x25480858: 2F800000 cmpi cr7,r0,0
1572 0x25480AF8: 7F895840 cmpl cr7,r9,r11
1616 0x25480AF8: 7F895840 cmpl cr7,r9,r11
1915 0x25471CB8: 2F8A0000 cmpi cr7,r10,0
2039 0x25471D04: 7F8BF840 cmpl cr7,r11,r31
2081 0x25471D1C: 7F8BF840 cmpl cr7,r11,r31
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DREADME.txt59 cmplw cr7, r3, r4
313 1) cmpwi cr7, r3, 8
342 cmpw cr7, r3, r4
802 cmplw cr7, r2, r3
820 fcmpu cr7, f1, f2
830 fcmpu cr7,f1,f2
DPPCRegisterInfo.td246 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
/external/llvm/lib/Target/PowerPC/
DREADME.txt25 cmplw cr7, r3, r4
486 cmplw cr7, r2, r3
504 fcmpu cr7, f1, f2
514 fcmpu cr7,f1,f2
DPPCRegisterInfo.td201 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
/external/v8/src/s390/
Dmacro-assembler-s390.h182 CRegister cr = cr7);
1120 CRegister cr = cr7);
1330 void Assert(Condition cond, BailoutReason reason, CRegister cr = cr7);
1334 void Check(Condition cond, BailoutReason reason, CRegister cr = cr7);
1797 CRegister cr = cr7);
Dassembler-s390.h270 const CRegister cr7 = {7}; variable
1206 int32_t code = kDefaultStopCode, CRegister cr = cr7);
/external/v8/src/full-codegen/
Dfull-codegen.h290 CRegister cr = cr7);
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.td255 def CR7 : Register<"cr7">;
/external/v8/src/compiler/ppc/
Dcode-generator-ppc.cc1730 CRegister cr = cr7; in AssembleArchInstruction()
1757 CRegister cr = cr7; in AssembleArchInstruction()
/external/elfutils/tests/
Dtestfile44.expect.bz21testfile44.o: elf32-elf_i386 2 3Disassembly of section .text: 4 5 0 ...
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td291 def CR7 : X86Reg<"cr7", 7>;
/external/v8/src/arm/
Dassembler-arm.cc2300 mcr(p15, 0, r0, cr7, cr10, 5); in dmb()
2312 mcr(p15, 0, r0, cr7, cr10, 4); in dsb()
2324 mcr(p15, 0, r0, cr7, cr5, 4); in isb()

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