| /external/llvm/test/CodeGen/NVPTX/ |
| D | convert-fp.ll | 6 ; CHECK: cvt.rzi.u16.f32 %rs{{[0-9]+}}, %f{{[0-9]+}};
13 ; CHECK: cvt.rzi.u16.f64 %rs{{[0-9]+}}, %fd{{[0-9]+}};
20 ; CHECK: cvt.rzi.u32.f32 %r{{[0-9]+}}, %f{{[0-9]+}};
27 ; CHECK: cvt.rzi.u32.f64 %r{{[0-9]+}}, %fd{{[0-9]+}};
35 ; CHECK: cvt.rzi.u64.f32 %rd{{[0-9]+}}, %f{{[0-9]+}};
42 ; CHECK: cvt.rzi.u64.f64 %rd{{[0-9]+}}, %fd{{[0-9]+}};
49 ; CHECK: cvt.rn.f32.u16 %f{{[0-9]+}}, %rs{{[0-9]+}};
56 ; CHECK: cvt.rn.f32.u32 %f{{[0-9]+}}, %r{{[0-9]+}};
63 ; CHECK: cvt.rn.f32.u64 %f{{[0-9]+}}, %rd{{[0-9]+}};
70 ; CHECK: cvt.rn.f32.f64 %f{{[0-9]+}}, %fd{{[0-9]+}};
[all …]
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| D | fp16.ll | 9 ; CHECK: cvt.f32.f16
12 %cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
13 store float %cvt, float addrspace(1)* %out, align 4
19 ; CHECK: cvt.f64.f16
22 %cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
23 store double %cvt, double addrspace(1)* %out, align 4
29 ; CHECK: cvt.rn.f16.f32
32 %cvt = call i16 @llvm.convert.to.fp16.f32(float %val) nounwind readnone
33 store i16 %cvt, i16 addrspace(1)* %out, align 4
39 ; CHECK: cvt.rn.f16.f64
[all …]
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| D | sext-in-reg.ll | 7 ; CHECK: cvt.s64.s8
8 ; CHECK: cvt.s64.s8
26 ; CHECK: cvt.s64.s32
27 ; CHECK: cvt.s64.s32
44 ; CHECK: cvt.s64.s16
45 ; CHECK: cvt.s64.s16
62 ; CHECK: cvt.s32.s8
63 ; CHECK: cvt.s32.s8
80 ; CHECK: cvt.s32.s16
81 ; CHECK: cvt.s32.s16
[all …]
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| D | extloadv.ll | 8 ; CHECK: cvt.f64.f32
9 ; CHECK: cvt.f64.f32
10 ; CHECK: cvt.f64.f32
11 ; CHECK: cvt.f64.f32
|
| D | i1-int-to-fp.ll | 6 ; CHECK: cvt.rn.f32.u32
15 ; CHECK: cvt.rn.f32.s32
24 ; CHECK: cvt.rn.f64.u32
33 ; CHECK: cvt.rn.f64.s32
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | cvt_f32_ubyte.ll | 12 %cvt = uitofp i8 %load to float
13 store float %cvt, float addrspace(1)* %out, align 4
24 %cvt = uitofp <2 x i8> %load to <2 x float>
25 store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
38 %cvt = uitofp <3 x i8> %load to <3 x float>
39 store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
54 %cvt = uitofp <4 x i8> %load to <4 x float>
55 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
78 %cvt = uitofp <4 x i8> %load to <4 x float>
79 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
[all …]
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| D | trunc-store-f64-to-f16.ll | 8 %cvt = fptrunc double %val to half
9 store half %cvt, half addrspace(1)* %out
17 %cvt = fptrunc <2 x double> %val to <2 x half>
18 store <2 x half> %cvt, <2 x half> addrspace(1)* %out
26 %cvt = fptrunc <3 x double> %val to <3 x half>
27 store <3 x half> %cvt, <3 x half> addrspace(1)* %out
35 %cvt = fptrunc <4 x double> %val to <4 x half>
36 store <4 x half> %cvt, <4 x half> addrspace(1)* %out
44 %cvt = fptrunc <8 x double> %val to <8 x half>
45 store <8 x half> %cvt, <8 x half> addrspace(1)* %out
[all …]
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| D | cvt_flr_i32_f32.ll | 15 %cvt = fptosi float %floor to i32
16 store i32 %cvt, i32 addrspace(1)* %out
28 %cvt = fptosi float %floor to i32
29 store i32 %cvt, i32 addrspace(1)* %out
41 %cvt = fptosi float %floor to i32
42 store i32 %cvt, i32 addrspace(1)* %out
54 %cvt = fptosi float %floor to i32
55 store i32 %cvt, i32 addrspace(1)* %out
68 %cvt = fptosi float %floor to i32
69 store i32 %cvt, i32 addrspace(1)* %out
[all …]
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| D | cvt_rpi_i32_f32.ll | 15 %cvt = fptosi float %floor to i32
16 store i32 %cvt, i32 addrspace(1)* %out
28 %cvt = fptosi float %floor to i32
29 store i32 %cvt, i32 addrspace(1)* %out
44 %cvt = fptosi float %floor to i32
45 store i32 %cvt, i32 addrspace(1)* %out
63 %cvt = fptosi float %floor to i32
64 store i32 %cvt, i32 addrspace(1)* %out
77 %cvt = fptoui float %floor to i32
78 store i32 %cvt, i32 addrspace(1)* %out
|
| D | half.ll | 275 %cvt = fpext half %val to float
276 store float %cvt, float addrspace(1)* %out
289 %cvt = fpext <2 x half> %val to <2 x float>
290 store <2 x float> %cvt, <2 x float> addrspace(1)* %out
297 %cvt = fpext <3 x half> %val to <3 x float>
298 store <3 x float> %cvt, <3 x float> addrspace(1)* %out
305 %cvt = fpext <4 x half> %val to <4 x float>
306 store <4 x float> %cvt, <4 x float> addrspace(1)* %out
313 %cvt = fpext <8 x half> %val to <8 x float>
314 store <8 x float> %cvt, <8 x float> addrspace(1)* %out
[all …]
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| D | fp16_to_fp.ll | 13 %cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
14 store float %cvt, float addrspace(1)* %out, align 4
26 %cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
27 store double %cvt, double addrspace(1)* %out, align 4
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/PTX/ |
| D | cvt.ll | 71 ; CHECK: cvt.u16.u32 %ret{{[0-9]+}}, %r{{[0-9]+}};
78 ; CHECK: cvt.u16.u64 %ret{{[0-9]+}}, %rd{{[0-9]+}};
85 ; CHECK: cvt.rzi.u16.f32 %ret{{[0-9]+}}, %f{{[0-9]+}};
92 ; CHECK: cvt.rzi.u16.f64 %ret{{[0-9]+}}, %fd{{[0-9]+}};
108 ; CHECK: cvt.u32.u16 %ret{{[0-9]+}}, %rh{{[0-9]+}};
115 ; CHECK: cvt.u32.u64 %ret{{[0-9]+}}, %rd{{[0-9]+}};
122 ; CHECK: cvt.rzi.u32.f32 %ret{{[0-9]+}}, %f{{[0-9]+}};
129 ; CHECK: cvt.rzi.u32.f64 %ret{{[0-9]+}}, %fd{{[0-9]+}};
145 ; CHECK: cvt.u64.u16 %ret{{[0-9]+}}, %rh{{[0-9]+}};
152 ; CHECK: cvt.u64.u32 %ret{{[0-9]+}}, %r{{[0-9]+}};
[all …]
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| /external/opencv/cv/src/ |
| D | cvsamplers.cpp | 601 worktype, cast_macro, cvt ) \ argument
634 worktype p0 = cvt(ptr[0])*a1 + cvt(ptr[1])*a; \
635 worktype p1 = cvt(ptr[src_step])*a1 + cvt(ptr[src_step+1])*a;\
659 p0 = cvt(ptr0[ixs])*a1 + cvt(ptr0[ixs+1])*a; \
660 p1 = cvt(ptr1[ixs])*a1 + cvt(ptr1[ixs+1])*a; \
665 p0 = cvt(ptr0[ixs]); p1 = cvt(ptr1[ixs]); \
677 worktype, cast_macro, cvt ) \ argument
714 p0 = cvt(ptr[0])*a1 + cvt(ptr[3])*a; \
715 p1 = cvt(ptr[src_step])*a1 + cvt(ptr[src_step+3])*a; \
718 p0 = cvt(ptr[1])*a1 + cvt(ptr[4])*a; \
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | vec_fp_to_int.ll | 34 %cvt = fptosi <2 x double> %a to <2 x i64>
35 ret <2 x i64> %cvt
60 %cvt = fptosi <2 x double> %a to <2 x i32>
61 …%ext = shufflevector <2 x i32> %cvt, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 unde…
89 %cvt = fptosi <4 x double> %ext to <4 x i32>
90 ret <4 x i32> %cvt
129 %cvt = fptosi <4 x double> %a to <4 x i64>
130 ret <4 x i64> %cvt
158 %cvt = fptosi <4 x double> %a to <4 x i32>
159 ret <4 x i32> %cvt
[all …]
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| D | isint.ll | 10 ; CHECK: cvt
12 ; CHECK-NEXT: cvt
27 ; CHECK: cvt
29 ; CHECK-NEXT: cvt
44 ; CHECK: cvt
46 ; CHECK-NEXT: cvt
|
| D | vec_int_to_fp.ll | 36 %cvt = sitofp <2 x i64> %a to <2 x double>
37 ret <2 x double> %cvt
51 %cvt = sitofp <2 x i32> %shuf to <2 x double>
52 ret <2 x double> %cvt
67 %cvt = sitofp <4 x i32> %a to <4 x double>
68 %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
86 %cvt = sitofp <2 x i16> %shuf to <2 x double>
87 ret <2 x double> %cvt
113 %cvt = sitofp <8 x i16> %a to <8 x double>
114 %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
[all …]
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| D | sse-intrinsics-fast-isel-x86_64.ll | 12 %cvt = sitofp i64 %a1 to float
13 %res = insertelement <4 x float> %a0, float %cvt, i32 0
32 %cvt = extractelement <4 x float> %a0, i32 0
33 %res = fptosi float %cvt to i64
|
| D | f16c-intrinsics-fast-isel.ll | 33 %cvt = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %ins7)
34 %res = extractelement <4 x float> %cvt, i32 0
61 %cvt = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %ins3, i32 0)
62 %res = extractelement <8 x i16> %cvt, i32 0
106 %cvt = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)
107 %res = bitcast <8 x i16> %cvt to <2 x i64>
123 %cvt = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)
124 %res = bitcast <8 x i16> %cvt to <2 x i64>
|
| /external/llvm/test/MC/Mips/ |
| D | micromips-fpu-instructions.s | 32 # CHECK-EL: cvt.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x09]
33 # CHECK-EL: cvt.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x49]
48 # CHECK-EL: cvt.d.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x13]
49 # CHECK-EL: cvt.d.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x33]
50 # CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b]
51 # CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b]
97 # CHECK-EB: cvt.w.s $f6, $f8 # encoding: [0x54,0xc8,0x09,0x3b]
98 # CHECK-EB: cvt.w.d $f6, $f8 # encoding: [0x54,0xc8,0x49,0x3b]
113 # CHECK-EB: cvt.d.s $f6, $f8 # encoding: [0x54,0xc8,0x13,0x7b]
114 # CHECK-EB: cvt.d.w $f6, $f8 # encoding: [0x54,0xc8,0x33,0x7b]
[all …]
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| D | mips-fpu-instructions.s | 124 # CHECK: cvt.d.s $f6, $f7 # encoding: [0xa1,0x39,0x00,0x46]
125 # CHECK: cvt.d.w $f12, $f14 # encoding: [0x21,0x73,0x80,0x46]
126 # CHECK: cvt.s.d $f12, $f14 # encoding: [0x20,0x73,0x20,0x46]
127 # CHECK: cvt.s.w $f6, $f7 # encoding: [0xa0,0x39,0x80,0x46]
128 # CHECK: cvt.w.d $f12, $f14 # encoding: [0x24,0x73,0x20,0x46]
129 # CHECK: cvt.w.s $f6, $f7 # encoding: [0xa4,0x39,0x00,0x46]
131 cvt.d.s $f6,$f7
132 cvt.d.w $f12,$f14
133 cvt.s.d $f12,$f14
134 cvt.s.w $f6,$f7
[all …]
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| /external/llvm/test/CodeGen/Mips/ |
| D | int-to-float-conversion.ll | 10 ; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
20 ; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
23 ; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
33 ; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
43 ; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
|
| /external/valgrind/VEX/priv/ |
| D | guest_mips_helpers.c | 1244 ASM_VOLATILE_UNARY32(cvt.d.s) in mips_dirtyhelper_calculate_FCSR_fp32()
1247 ASM_VOLATILE_UNARY32(cvt.d.w) in mips_dirtyhelper_calculate_FCSR_fp32()
1250 ASM_VOLATILE_UNARY32(cvt.s.w) in mips_dirtyhelper_calculate_FCSR_fp32()
1253 ASM_VOLATILE_UNARY32_DOUBLE(cvt.s.d) in mips_dirtyhelper_calculate_FCSR_fp32()
1256 ASM_VOLATILE_UNARY32(cvt.w.s) in mips_dirtyhelper_calculate_FCSR_fp32()
1259 ASM_VOLATILE_UNARY32_DOUBLE(cvt.w.d) in mips_dirtyhelper_calculate_FCSR_fp32()
1273 ASM_VOLATILE_UNARY32_DOUBLE(cvt.d.l) in mips_dirtyhelper_calculate_FCSR_fp32()
1276 ASM_VOLATILE_UNARY32(cvt.l.s) in mips_dirtyhelper_calculate_FCSR_fp32()
1279 ASM_VOLATILE_UNARY32_DOUBLE(cvt.l.d) in mips_dirtyhelper_calculate_FCSR_fp32()
1282 ASM_VOLATILE_UNARY32_DOUBLE(cvt.s.l) in mips_dirtyhelper_calculate_FCSR_fp32()
[all …]
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | isint.ll | 5 ; CHECK: cvt
7 ; CHECK-NEXT: cvt
20 ; CHECK: cvt
22 ; CHECK-NEXT: cvt
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 33 cvt.d.s $f22,$f28
34 cvt.d.w $f26,$f11
35 cvt.s.d $f26,$f8
36 cvt.s.w $f22,$f15
37 cvt.w.d $f20,$f14
38 cvt.w.s $f20,$f24
138 # CHECK: cvt.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x24]
150 # CHECK: cvt.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x24]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | valid.s | 117 cvt.l.s $f3, $f4 # CHECK: cvt.l.s $f3, $f4 # encoding: [0x54,0x64,0x01,0x3b]
118 cvt.l.d $f3, $f4 # CHECK: cvt.l.d $f3, $f4 # encoding: [0x54,0x64,0x41,0x3b]
119 cvt.w.s $f3, $f4 # CHECK: cvt.w.s $f3, $f4 # encoding: [0x54,0x64,0x09,0x3b]
120 cvt.w.d $f3, $f4 # CHECK: cvt.w.d $f3, $f4 # encoding: [0x54,0x64,0x49,0x3b]
121 cvt.d.s $f2, $f4 # CHECK: cvt.d.s $f2, $f4 # encoding: [0x54,0x44,0x13,0x7b]
122 cvt.d.w $f2, $f4 # CHECK: cvt.d.w $f2, $f4 # encoding: [0x54,0x44,0x33,0x7b]
123 cvt.d.l $f2, $f4 # CHECK: cvt.d.l $f2, $f4 # encoding: [0x54,0x44,0x53,0x7b]
124 cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b]
125 cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b]
126 cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b]
|