| /external/llvm/test/MC/Mips/ |
| D | macro-ddivu.s | 6 ddivu $25,$11
8 # CHECK-NOTRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
12 ddivu $24,$12
14 # CHECK-NOTRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
18 ddivu $25,$0
20 # CHECK-NOTRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
24 ddivu $0,$9
26 # CHECK-NOTRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
30 ddivu $0,$0
32 # CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
[all …]
|
| D | macro-ddiv-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| D | macro-ddivu-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| /external/llvm/test/CodeGen/Mips/ |
| D | mips64muldiv.ll | 44 ; ACC: ddivu $zero, $4, $5
46 ; GPR: ddivu $2, $4, $5
64 ; ACC: ddivu $zero, $4, $5
|
| D | mips64instrs.ll | 140 ; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
144 ; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
172 ; ACCMULDIV: ddivu $zero, $4, $5
|
| D | divrem.ll | 285 ; GPR64: ddivu $2, $4, $5
366 ; ACC64: ddivu $zero, $4, $5
373 ; GPR64-DAG: ddivu $2, $4, $5
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | udiv.ll | 130 ; GP64-NOT-R6: ddivu $zero, $4, $5
134 ; 64R6: ddivu $2, $4, $5
139 ; MM64: ddivu $2, $4, $5
|
| D | urem.ll | 186 ; GP64-NOT-R6: ddivu $zero, $4, $5
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | mips64instrs.ll | 97 ; CHECK: ddivu $zero
113 ; CHECK: ddivu $zero
|
| /external/valgrind/none/tests/mips64/ |
| D | arithmetic_instruction.stdout.exp-mips64 | 9467 ddivu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
9468 ddivu $v0, $v1 :: rs 0x12bd6aa, rt 0xa2a6ec661ba84121, HI 0x12bd6aa, LO 0x0
9469 ddivu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
9470 ddivu $v0, $v1 :: rs 0x7e876382d2ab13, rt 0x614d9b445f12236b, HI 0x7e876382d2ab13, LO 0x0
9471 ddivu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
9472 ddivu $v0, $v1 :: rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75, HI 0x20183c0c843a7609, LO 0x2
9473 ddivu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
9474 ddivu $v0, $v1 :: rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666, HI 0x4f679f17a89fef95, LO 0x1
9475 ddivu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
9476 ddivu $v0, $v1 :: rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17, HI 0x42b0c0a28677b502, LO 0x0
[all …]
|
| D | arithmetic_instruction.stdout.exp-mips64r2 | 9467 ddivu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
9468 ddivu $v0, $v1 :: rs 0x12bd6aa, rt 0xa2a6ec661ba84121, HI 0x12bd6aa, LO 0x0
9469 ddivu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
9470 ddivu $v0, $v1 :: rs 0x7e876382d2ab13, rt 0x614d9b445f12236b, HI 0x7e876382d2ab13, LO 0x0
9471 ddivu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
9472 ddivu $v0, $v1 :: rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75, HI 0x20183c0c843a7609, LO 0x2
9473 ddivu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
9474 ddivu $v0, $v1 :: rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666, HI 0x4f679f17a89fef95, LO 0x1
9475 ddivu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
9476 ddivu $v0, $v1 :: rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17, HI 0x42b0c0a28677b502, LO 0x0
[all …]
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips3.s | 31 # ddivu has been re-encoded. See valid.s
|
| D | invalid-mips64.s | 52 # ddivu has been re-encoded. See valid.s
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | invalid.s | 79 ddivu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
80 ddivu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
81 ddivu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| D | valid.s | 59 ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98]
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 21 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
|
| D | invalid-mips5.s | 21 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
|
| D | invalid-mips4.s | 21 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-el.txt | 84 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
226 0x1f 0x00 0x38 0x01 # CHECK: ddivu $zero, $9, $24
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 29 class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
129 class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
|
| D | Mips64r6InstrInfo.td | 65 class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-mips64r2-el.txt | 90 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
247 0x1f 0x00 0x38 0x01 # CHECK: ddivu $zero, $9, $24
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 169 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | invalid-mips3.s | 25 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
| D | invalid-mips4.s | 23 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|