| /external/valgrind/none/tests/mips64/ |
| D | extract_insert_bit_field.stdout.exp-mips64r2 | 878 dextu :: in 0x0, in1 0x0, out 0x0, pos: 32, size: 1
879 dextu :: in 0x0, in1 0xffffffffffffffff, out 0x0, pos: 32, size: 1
880 dextu :: in 0x0, in1 0x98765432, out 0x0, pos: 32, size: 1
881 dextu :: in 0x0, in1 0xffffffffff865421, out 0x0, pos: 32, size: 1
882 dextu :: in 0xffffffffffffffff, in1 0x0, out 0x1, pos: 32, size: 1
883 dextu :: in 0xffffffffffffffff, in1 0xffffffffffffffff, out 0x1, pos: 32, size: 1
884 dextu :: in 0xffffffffffffffff, in1 0x98765432, out 0x1, pos: 32, size: 1
885 dextu :: in 0xffffffffffffffff, in1 0xffffffffff865421, out 0x1, pos: 32, size: 1
886 dextu :: in 0x98765432, in1 0x0, out 0x1, pos: 32, size: 1
887 dextu :: in 0x98765432, in1 0xffffffffffffffff, out 0x1, pos: 32, size: 1
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | mips64extins.ll | 21 define i64 @dextu(i64 %i) nounwind readnone {
23 ; CHECK-LABEL: dextu:
24 ; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
|
| D | fcopysign.ll | 30 ; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
|
| D | fcopysign-f32-f64.ll | 25 ; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
|
| /external/llvm/test/MC/Mips/ |
| D | mips64extins.s | 5 dextu $2, $4, 34, 6 # CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
|
| /external/llvm/test/Object/Mips/ |
| D | feature.test | 7 CHECK: dextu:
|
| /external/llvm/test/MC/Mips/mips64/ |
| D | invalid-mips64r2.s | 11 …dextu $1, $2, 33, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | invalid.s | 33 dextu $2, $3, 31, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
34 dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
35 dextu $2, $3, 32, 0 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
36 dextu $2, $3, 32, 33 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
|
| D | valid.s | 24 dextu $9, $6, 35, 7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x59,0x26,0x30,0xd4]
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 114 class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
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| D | Mips64InstrInfo.td | 319 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
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| /external/llvm/test/MC/Disassembler/Mips/micromips64r6/ |
| D | valid.txt | 42 0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7
|
| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 902 void dextu(Register rt, Register rs, uint16_t pos, uint16_t size);
|
| D | assembler-mips64.cc | 2479 void Assembler::dextu(Register rt, Register rs, uint16_t pos, uint16_t size) { in dextu() function in v8::internal::Assembler
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| D | macro-assembler-mips64.cc | 1800 dextu(rt, rs, pos, size); in Dextu()
|