Searched refs:dmodu (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/test/CodeGen/Mips/ |
| D | mips64muldiv.ll | 66 ; GPR: dmodu $2, $4, $5
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| D | divrem.ll | 307 ; GPR64: dmodu $2, $4, $5
377 ; GPR64: dmodu $[[R0:[0-9]+]], $4, $5
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| D | mips64instrs.ll | 176 ; GPRMULDIV: dmodu $2, $4, $5
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| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | urem.ll | 190 ; 64R6: dmodu $2, $4, $5
195 ; MM64: dmodu $2, $4, $5
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| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | invalid.s | 82 dmodu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
83 dmodu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
84 dmodu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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| D | valid.s | 60 dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0xd8]
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 30 class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
130 class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, urem>;
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| D | Mips64r6InstrInfo.td | 68 class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
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| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| D | valid-mips64r6-el.txt | 112 0xdf 0x10 0x64 0x00 # CHECK: dmodu $2, $3, $4
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| D | valid-mips64r6.txt | 30 0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4
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| /external/llvm/test/MC/Disassembler/Mips/micromips64r6/ |
| D | valid.txt | 47 0x58 0xa4 0x19 0xd8 # CHECK: dmodu $3, $4, $5
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| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 744 void dmodu(Register rd, Register rs, Register rt);
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| D | macro-assembler-mips64.cc | 1001 dmodu(rd, rs, rt.rm()); in Dmodu()
1006 dmodu(rd, rs, at); in Dmodu()
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| D | assembler-mips64.cc | 1745 void Assembler::dmodu(Register rd, Register rs, Register rt) { in dmodu() function in v8::internal::Assembler
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