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/external/valgrind/none/tests/mips64/
Drotate_swap.stdout.exp-mips64r22 drotr :: in 0x2000ffffffffffff, out 0xffff2000ffffffff, SA 16
3 drotr :: in 0xffff0000ffffffff, out 0xffffffff0000ffff, SA 16
4 drotr :: in 0x2000ffffffffffff, out 0xff2000ffffffffff, SA 8
5 drotr :: in 0x2000ffffffffffff, out 0xf2000fffffffffff, SA 4
6 drotr :: in 0x2000ffffffffffff, out 0xf90007ffffffffff, SA 5
7 drotr :: in 0x31415927ffffffff, out 0xffcc505649ffffff, SA 10
8 drotr :: in 0x2000ffffffffffff, out 0xf2000fffffffffff, SA 4
9 drotr :: in 0x2000ffffffffffff, out 0x2000ffffffffffff, SA 0
10 drotr :: in 0xeeeeffffffffffff, out 0xffffeeeeffffffff, SA 16
11 drotr :: in 0x2000ffffffffbbbb, out 0xffff77764001ffff, SA 31
[all …]
Dshift_instructions.stdout.exp-mips64r21 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
2 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
3 drotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
4 drotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
5 drotr $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
6 drotr $t2, $t3, 0x1f :: rt 0x257ad5400000000, rs 0x12bd6aa, imm 0x001f
7 drotr $a0, $a1, 0x0f :: rt 0xad54000000000257, rs 0x12bd6aa, imm 0x000f
8 drotr $s0, $s1, 0x03 :: rt 0x4000000000257ad5, rs 0x12bd6aa, imm 0x0003
9 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
10 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
/external/llvm/test/MC/Mips/
Drotations64.s111 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
131 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa]
136 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
139 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
159 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa]
164 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
182 # CHECK-64R: drotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x7a]
185 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
190 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
195 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa]
[all …]
Dmips_directives.s76 # CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba]
78 drotr $9, $6, 30
Dmips64-alu-instructions.s76 # CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00]
101 drotr $9, $6, 20
/external/llvm/test/CodeGen/Mips/
Dmips64shift.ll91 ; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
100 ; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
/external/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s15 …drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips5/
Dinvalid-mips64r2.s14 …drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s96 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
97 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s96 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
97 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s96 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x…
97 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dmips64shift.ll88 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt125 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
126 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
272 0xba 0xa1 0x3b 0x00 # CHECK: drotr $20, $27, 6
Dvalid-mips64r2.txt55 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
59 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
62 0x00 0x3b 0xa1 0xba # CHECK: drotr $20, $27, 6
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-mips64r3-el.txt122 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
123 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
Dvalid-mips64r3.txt52 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
56 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
59 0x00 0x3b 0xa1 0xba # CHECK: drotr $20, $27, 6
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-mips64r5-el.txt122 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
123 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
Dvalid-mips64r5.txt52 0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
56 0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
59 0x00 0x3b 0xa1 0xba # CHECK: drotr $20, $27, 6
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td60 class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>;
258 class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm6, II_DROTR,
DMips64InstrInfo.td166 def DROTR : StdMMR6Rel, shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR,
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMips64InstrInfo.td128 def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>;
/external/llvm/test/MC/Mips/micromips64r6/
Dvalid.s300 drotr $5, $10, 8 # CHECK: drotr $5, $10, 8 # encoding: [0x58,0xaa,0x40,0xc0]
Dinvalid.s290 …drotr $5, $10, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immedi…
291 …drotr $5, $10, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immedi…
/external/llvm/test/MC/Disassembler/Mips/micromips64r6/
Dvalid.txt289 0x58 0xaa 0x40 0xc0 # CHECK: drotr $5, $10, 8
/external/v8/src/mips64/
Dassembler-mips64.h795 void drotr(Register rd, Register rt, uint16_t sa);

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