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Searched refs:ds_add_u32 (Results 1 – 6 of 6) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Datomic_load_add.ll7 ; SI: ds_add_u32
15 ; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
Dlocal-atomics.ll331 ; GCN: ds_add_u32 [[VPTR]], [[DATA]]
339 ; GCN: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
348 ; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}}
349 ; CIVI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
361 ; GCN: ds_add_u32 v{{[0-9]+}}, [[ONE]]
370 ; GCN: ds_add_u32 v{{[0-9]+}}, [[ONE]] offset:16
379 ; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}}
380 ; CIVI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
/external/llvm/test/MC/AMDGPU/
Dds-err.s6 ds_add_u32 v2, v4 offset:1000000000 label
Dds.s9 ds_add_u32 v2, v4 offset:16 label
53 ds_add_u32 v2, v4 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dds_vi.txt3 # VI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
24 # VI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td770 defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>;
802 defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;