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Searched refs:dsra (Results 1 – 25 of 45) sorted by relevance

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/external/valgrind/none/tests/mips64/
Dshift_instructions.stdout.exp-mips644609 dsra $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
4610 dsra $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
4611 dsra $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
4612 dsra $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
4613 dsra $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
4614 dsra $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
4615 dsra $a0, $a1, 0x0f :: rt 0x257, rs 0x12bd6aa, imm 0x000f
4616 dsra $s0, $s1, 0x03 :: rt 0x257ad5, rs 0x12bd6aa, imm 0x0003
4617 dsra $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
4618 dsra $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
Dshift_instructions.stdout.exp-mips64r29217 dsra $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
9218 dsra $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
9219 dsra $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
9220 dsra $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
9221 dsra $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000
9222 dsra $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
9223 dsra $a0, $a1, 0x0f :: rt 0x257, rs 0x12bd6aa, imm 0x000f
9224 dsra $s0, $s1, 0x03 :: rt 0x257ad5, rs 0x12bd6aa, imm 0x0003
9225 dsra $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
9226 dsra $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
/external/llvm/test/CodeGen/Mips/
Dmips64shift.ll34 ; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
55 ; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
/external/llvm/test/MC/Mips/mips3/
Dvalid.s89 …dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
90 …dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
91 …dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s34 …dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
35 …dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
36 …dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
Dinvalid-mips5.s31 …dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
32 …dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
33 …dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips4.s32 …dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
33 …dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
34 …dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips64/
Dvalid.s100 …dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
101 …dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
102 …dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x…
/external/llvm/test/MC/Mips/mips4/
Dvalid.s93 …dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
94 …dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
95 …dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x…
/external/llvm/test/MC/Mips/mips5/
Dvalid.s93 …dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
94 …dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
95 …dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x…
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s109 …dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
110 …dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
111 …dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x…
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s109 …dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
110 …dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
111 …dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x…
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s109 …dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0x…
110 …dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0x…
111 …dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x…
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dashr.ll180 ; M3: dsra $2, $4, 63
194 ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63
203 ; 64R6: dsra $[[T5:[0-9]+]], $4, 63
/external/llvm/test/MC/Mips/
Dmips64shift.ll16 ; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s38 …dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
39 …dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
40 …dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips4.s34 …dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
35 …dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
36 …dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips5.s33 …dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
34 …dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
35 …dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dmips64shift.ll33 ; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-el.txt97 0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
98 0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
233 0xbb 0x0f 0x01 0x00 # CHECK: dsra $1, $1, 30
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt103 0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
104 0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
254 0xbb 0x0f 0x01 0x00 # CHECK: dsra $1, $1, 30
/external/llvm/test/MC/Disassembler/Mips/mips3/
Dvalid-mips3-el.txt79 0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
80 0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
Dvalid-mips3.txt34 0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10
40 0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
/external/llvm/test/MC/Disassembler/Mips/mips4/
Dvalid-mips4-el.txt83 0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
84 0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-mips64r3-el.txt100 0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
101 0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10

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