| /external/llvm/test/MC/Mips/ |
| D | rotations64.s | 106 # CHECK-64: dsrl32 $4, $4, 31 # encoding: [0x00,0x04,0x27,0xfe]
114 # CHECK-64: dsrl32 $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfe]
119 # CHECK-64: dsrl32 $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7e]
124 # CHECK-64: dsrl32 $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3e]
142 # CHECK-64: dsrl32 $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfe]
147 # CHECK-64: dsrl32 $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7e]
152 # CHECK-64: dsrl32 $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3e]
197 # CHECK-64: dsrl32 $1, $5, 0 # encoding: [0x00,0x05,0x08,0x3e]
202 # CHECK-64: dsrl32 $1, $5, 1 # encoding: [0x00,0x05,0x08,0x7e]
207 # CHECK-64: dsrl32 $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xfe]
[all …]
|
| D | mips64shift.ll | 44 ; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8
|
| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.stdout.exp-mips64 | 11265 dsrl32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
11266 dsrl32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
11267 dsrl32 $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
11268 dsrl32 $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
11269 dsrl32 $t0, $t1, 0x00 :: rt 0x0, rs 0x12bd6aa, imm 0x0000
11270 dsrl32 $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
11271 dsrl32 $a0, $a1, 0x0f :: rt 0x0, rs 0x12bd6aa, imm 0x000f
11272 dsrl32 $s0, $s1, 0x03 :: rt 0x0, rs 0x12bd6aa, imm 0x0003
11273 dsrl32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
11274 dsrl32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
|
| D | shift_instructions.stdout.exp-mips64r2 | 15873 dsrl32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
15874 dsrl32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
15875 dsrl32 $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
15876 dsrl32 $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
15877 dsrl32 $t0, $t1, 0x00 :: rt 0x0, rs 0x12bd6aa, imm 0x0000
15878 dsrl32 $t2, $t3, 0x1f :: rt 0x0, rs 0x12bd6aa, imm 0x001f
15879 dsrl32 $a0, $a1, 0x0f :: rt 0x0, rs 0x12bd6aa, imm 0x000f
15880 dsrl32 $s0, $s1, 0x03 :: rt 0x0, rs 0x12bd6aa, imm 0x0003
15881 dsrl32 $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
15882 dsrl32 $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
[all …]
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 98 …dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
99 …dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
|
| /external/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 109 …dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
110 …dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 102 …dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
103 …dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 102 …dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
103 …dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 118 …dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
119 …dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 118 …dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
119 …dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 118 …dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0x…
119 …dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0x…
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 43 …dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
44 …dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
|
| D | invalid-mips5.s | 40 …dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
41 …dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
|
| D | invalid-mips4.s | 41 …dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
42 …dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | mips64shift.ll | 61 ; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | invalid-mips3.s | 47 …dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
48 …dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
| D | invalid-mips4.s | 43 …dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
44 …dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
| D | invalid-mips5.s | 42 …dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
43 …dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| D | valid-mips3-el.txt | 88 0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
89 0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
|
| D | valid-mips3.txt | 28 0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23
37 0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| D | valid-mips4-el.txt | 92 0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
93 0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-mips64r3-el.txt | 109 0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
110 0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-mips64r5-el.txt | 109 0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
110 0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-el.txt | 106 0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
107 0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 68 class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>;
265 class DSRL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl32", uimm5, II_DSRL32>;
|