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Searched refs:f12 (Results 1 – 25 of 394) sorted by relevance

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/external/llvm/test/CodeGen/Mips/llvm-ir/
D	select-flt.ll	`81 ; M2: mov.s $f12, $f14 82 ; M3: mov.s $f12, $f13 85 ; M2-M3: mov.s $f0, $f12 88 ; CMOV-32: movn.s $f14, $f12, $[[T0]] 92 ; SEL-32: sel.s $f0, $f14, $f12 95 ; CMOV-64: movn.s $f13, $f12, $[[T0]] 99 ; SEL-64: sel.s $f0, $f13, $f12 102 ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]] 113 ; M2: c.olt.s $f12, $f14 114 ; M3: c.olt.s $f12, $f13 [all …]`
D	select-dbl.ll	`94 ; M2: mov.d $f12, $f14 97 ; M2: mov.d $f0, $f12 101 ; CMOV-32: movn.d $f14, $f12, $[[T1]] 106 ; SEL-32: sel.d $f0, $f14, $f12 111 ; M3: mov.d $f12, $f13 114 ; M3: mov.d $f0, $f12 117 ; CMOV-64: movn.d $f13, $f12, $[[T0]] 121 ; SEL-64: sel.d $f0, $f13, $f12 125 ; MM32R3: movn.d $f14, $f12, $[[T1]] 136 ; M2: c.olt.d $f12, $f14 [all …]`
/external/llvm/test/MC/Mips/
D	mips-fpu-instructions.s	9 # CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46] 11 # CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46] 13 # CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46] 15 # CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46] 17 # CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46] 19 # CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46] 21 # CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46] 23 # CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46] 25 # CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46] 27 # CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46] [all …]
/external/llvm/test/CodeGen/Mips/
D	fcmp.ll	`43 ; 32-C-DAG: c.eq.s $f12, $f14 47 ; 64-C-DAG: c.eq.s $f12, $f13 50 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 54 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 60 ; MM32R3-DAG: c.eq.s $f12, $f14 63 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 64 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 77 ; 32-C-DAG: c.ule.s $f12, $f14 81 ; 64-C-DAG: c.ule.s $f12, $f13 84 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 [all …]`
D	fmadd1.ll	26 ; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 32 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 37 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 42 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 50 ; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13 66 ; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 72 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 77 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14 82 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 [all …]
D	o32_cc.ll	`6 ; $f12, $f14 8 ; ALL-DAG: ldc1 $f12, %lo 18 ; $f12, $f14 20 ; ALL-DAG: lwc1 $f12, %lo 30 ; $f12, $f14 32 ; ALL-DAG: lwc1 $f12, %lo 42 ; $f12, $f14 44 ; ALL-DAG: ldc1 $f12, %lo 68 ; $f12, $6, stack 70 ; ALL-DAG: ldc1 $f12, %lo [all …]`
D	fpbr.ll	`12 ; 32-FCC: c.eq.s $f12, $f14 13 ; 64-FCC: c.eq.s $f12, $f13 16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14 17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13 47 ; 32-FCC: c.olt.s $f12, $f14 48 ; 64-FCC: c.olt.s $f12, $f13 51 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12 52 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12 77 ; 32-FCC: c.ole.s $f12, $f14 78 ; 64-FCC: c.ole.s $f12, $f13 [all …]`
D	no-odd-spreg.ll	`15 ; Clobber all except $f12 and $f13 18 ; allocator will choose $f12 and $f13 to avoid the spill/reload. 30 ; ODDSPREG: add.s $f13, $f12, ${{f[0-9]+}} 33 ; ODDSPREG: add.s $f0, $f12, $f13 35 ; NOODDSPREG: add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}} 38 ; NOODDSPREG: add.s $f0, $f12, $[[T1]] 42 ; Clobber all except $f12 and $f13 45 ; use $f12 and $f13. 54 ; ALL: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}} 55 ; ALL: add.d $f0, $f12, $[[T0]]`
D	mno-ldc1-sdc1.ll	151 ; 32R1-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 156 ; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 157 ; 32R2-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 161 ; 32R6-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 162 ; 32R6-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 166 ; 32R1-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 173 ; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 174 ; 32R2-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 180 ; 32R6-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 181 ; 32R6-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 [all …]
D	select.ll	`207 ; 32: movt.s $f14, $f12, $fcc0 213 ; 32R2: movt.s $f14, $f12, $fcc0 219 ; 32R6: sel.s $[[CC]], $f14, $f12 222 ; 64: movt.s $f13, $f12, $fcc0 226 ; 64R2: movt.s $f13, $f12, $fcc0 230 ; 64R6: sel.s $[[CC]], $f13, $f12 244 ; 32: movt.s $f14, $f12, $fcc0 250 ; 32R2: movt.s $f14, $f12, $fcc0 256 ; 32R6: sel.s $[[CC]], $f14, $f12 259 ; 64: movt.s $f13, $f12, $fcc0 [all …]`
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
D	o32_cc.ll	`6 ; $f12, $f14 7 ; CHECK: ldc1 $f12, %lo 17 ; $f12, $f14 18 ; CHECK: lwc1 $f12, %lo 28 ; $f12, $f14 29 ; CHECK: lwc1 $f12, %lo 39 ; $f12, $f14 40 ; CHECK: ldc1 $f12, %lo 63 ; $f12, $6, stack 66 ; CHECK: ldc1 $f12, %lo [all …]`
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D	field-extract-use-trunc.ll	`4 define i32 @test(i32 %f12) nounwind { 5 %tmp7.25 = lshr i32 %f12, 16 11 define i32 @test2(i32 %f12) nounwind { 12 %f11 = shl i32 %f12, 8 17 define i32 @test3(i32 %f12) nounwind { 18 %f11 = shl i32 %f12, 13 23 define i64 @test4(i64 %f12) nounwind { 24 %f11 = shl i64 %f12, 32 29 define i16 @test5(i16 %f12) nounwind { 30 %f11 = shl i16 %f12, 2 [all …]`
/external/llvm/test/CodeGen/X86/
D	field-extract-use-trunc.ll	`4 define i32 @test(i32 %f12) nounwind { 5 %tmp7.25 = lshr i32 %f12, 16 11 define i32 @test2(i32 %f12) nounwind { 12 %f11 = shl i32 %f12, 8 17 define i32 @test3(i32 %f12) nounwind { 18 %f11 = shl i32 %f12, 13 23 define i64 @test4(i64 %f12) nounwind { 24 %f11 = shl i64 %f12, 32 29 define i16 @test5(i16 %f12) nounwind { 30 %f11 = shl i16 %f12, 2 [all …]`
/external/llvm/test/MC/Disassembler/Mips/mips32r2/
D	valid-mips32r2-el.txt	5 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14 8 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14 26 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14 28 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14 30 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14 32 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14 34 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14 36 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14 38 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14 40 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14 [all …]
D	valid-mips32r2.txt	239 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 240 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 241 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 242 0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 243 0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 244 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 245 0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 246 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 247 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 248 0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 [all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r3/
D	valid-mips32r3-el.txt	2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14 5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14 23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14 25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14 27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14 29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14 31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14 33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14 35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14 37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14 [all …]
D	valid-mips32r3.txt	236 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 237 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 238 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 239 0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 240 0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 241 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 242 0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 243 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 244 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 245 0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 [all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r5/
D	valid-mips32r5-el.txt	2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14 5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14 23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14 25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14 27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14 29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14 31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14 33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14 35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14 37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14 [all …]
D	valid-mips32r5.txt	237 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 238 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 239 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 240 0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14 241 0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14 242 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 243 0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14 244 0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14 245 0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14 246 0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14 [all …]
/external/llvm/test/MC/Disassembler/Mips/mips32/
D	valid-mips32-el.txt	2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14 5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14 25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14 27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14 29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14 31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14 33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14 35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14 37 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14 39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14 [all …]
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
D	valid-mips64r3-el.txt	3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14 6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14 24 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14 26 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14 28 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14 30 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14 32 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14 34 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14 36 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14 38 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14 [all …]
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
D	valid-mips64r5-el.txt	3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14 6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14 24 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14 26 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14 28 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14 30 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14 32 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14 34 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14 36 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14 38 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14 [all …]
/external/llvm/test/MC/Disassembler/Mips/mips64/
D	valid-mips64-el.txt	2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14 5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14 23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14 25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14 27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14 29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14 31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14 33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14 35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14 37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14 [all …]
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
D	valid-mips64r2-el.txt	6 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14 9 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14 27 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14 29 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14 31 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14 33 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14 35 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14 37 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14 39 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14 41 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14 [all …]
/external/webrtc/webrtc/modules/audio_processing/aec/
D	aec_rdft_mips.c	272 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cft1st_128_mips() local 512 [f12] "=&f" (f12), [f13] "=&f" (f13), [f14] "=&f" (f14), in cft1st_128_mips() 521 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cftmdl_128_mips() local 630 f12 = rdft_w[5]; in cftmdl_128_mips() 714 [f12] "f" (f12), [f13] "f" (f13), [f14] "f" (f14) in cftmdl_128_mips() 718 f12 = rdft_w[7]; in cftmdl_128_mips() 801 [f12] "f" (f12), [f13] "f" (f13), [f14] "f" (f14) in cftmdl_128_mips() 929 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftfsub_128_mips() local 1041 [f9] "=&f" (f9), [f10] "=&f" (f10), [f11] "=&f" (f11), [f12] "=&f" (f12), in rftfsub_128_mips() 1056 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftbsub_128_mips() local [all …]

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