| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-fp-compare.s | 99 fcmle h10, h11, #0.0
100 fcmle s10, s11, #0.0
101 fcmle d20, d21, #0.0
102 fcmle h10, h11, #0
103 fcmle s10, s11, #0
104 fcmle d20, d21, #0x0
|
| D | neon-compare-instructions.s | 217 fcmle v3.4h, v12.4h, v8.4h
218 fcmle v31.8h, v28.8h, v29.8h
222 fcmle v31.4s, v28.4s, v29.4s
223 fcmle v3.2s, v12.2s, v8.2s
224 fcmle v17.2d, v13.2d, v15.2d
441 fcmle v3.4h, v20.4h, #0.0
442 fcmle v1.8h, v8.8h, #0.0
443 fcmle v1.4s, v8.4s, #0.0
444 fcmle v3.2s, v20.2s, #0.0
445 fcmle v7.2d, v13.2d, #0.0
[all …]
|
| D | fullfp16-neon-neg.s | 100 fcmle v3.4h, v12.4h, v8.4h
102 fcmle v31.8h, v28.8h, v29.8h
136 fcmle v3.4h, v20.4h, #0.0
138 fcmle v1.8h, v8.8h, #0.0
140 fcmle v3.4h, v20.4h, #0
142 fcmle v1.8h, v8.8h, #0
268 fcmle h10, h11, #0.0
270 fcmle h10, h11, #0
|
| D | neon-diagnostics.s | 564 fcmle v17.8h, v15.2d, v13.2d
700 fcmle v17.8h, v15.2d, #-1.0
701 fcmle v17.8h, v15.2d, #2
748 fcmle v17.2d, v15.2d, #15.0
749 fcmle v17.2d, v15.2d, #15
4691 fcmle h10, s11, #0.0
4692 fcmle d20, s21, #0.0
|
| D | arm64-advsimd.s | 746 fcmle.2s v0, v0, #0
765 ; CHECK: fcmle.2s v0, v0, #0.0 ; encoding: [0x00,0xd8,0xa0,0x2e]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | neon-compare-instructions.ll | 1910 ; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1918 ; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1926 ; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2064 ; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2074 ; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2083 ; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
|
| D | arm64-neon-compare-instructions.ll | 1179 ; CHECK: fcmle d0, d0, #0
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2781 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3168 def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" #
3169 "|fcmle.4h\t$dst, $src1, $src2}",
3171 def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" #
3172 "|fcmle.8h\t$dst, $src1, $src2}",
3175 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3176 "|fcmle.2s\t$dst, $src1, $src2}",
3178 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3179 "|fcmle.4s\t$dst, $src1, $src2}",
3181 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
[all …]
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 349 0x~~~~~~~~~~~~~~~~ 7ee0da38 fcmle d24, d17, #0.0
350 0x~~~~~~~~~~~~~~~~ 7ea0d90b fcmle s11, s8, #0.0
2205 0x~~~~~~~~~~~~~~~~ 6ee0d8c4 fcmle v4.2d, v6.2d, #0.0
2206 0x~~~~~~~~~~~~~~~~ 2ea0dbf8 fcmle v24.2s, v31.2s, #0.0
2207 0x~~~~~~~~~~~~~~~~ 6ea0dae8 fcmle v8.4s, v23.4s, #0.0
|
| D | log-disasm | 349 0x~~~~~~~~~~~~~~~~ 7ee0da38 fcmle d24, d17, #0.0
350 0x~~~~~~~~~~~~~~~~ 7ea0d90b fcmle s11, s8, #0.0
2205 0x~~~~~~~~~~~~~~~~ 6ee0d8c4 fcmle v4.2d, v6.2d, #0.0
2206 0x~~~~~~~~~~~~~~~~ 2ea0dbf8 fcmle v24.2s, v31.2s, #0.0
2207 0x~~~~~~~~~~~~~~~~ 6ea0dae8 fcmle v8.4s, v23.4s, #0.0
|
| D | log-all | 834 0x~~~~~~~~~~~~~~~~ 7ee0da38 fcmle d24, d17, #0.0
836 0x~~~~~~~~~~~~~~~~ 7ea0d90b fcmle s11, s8, #0.0
5713 0x~~~~~~~~~~~~~~~~ 6ee0d8c4 fcmle v4.2d, v6.2d, #0.0
5715 0x~~~~~~~~~~~~~~~~ 2ea0dbf8 fcmle v24.2s, v31.2s, #0.0
5717 0x~~~~~~~~~~~~~~~~ 6ea0dae8 fcmle v8.4s, v23.4s, #0.0
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 426 __ fcmle(d24, d17, 0.0); in GenerateTestSequenceFP() local
427 __ fcmle(s11, s8, 0.0); in GenerateTestSequenceFP() local
2557 __ fcmle(v4.V2D(), v6.V2D(), 0.0); in GenerateTestSequenceNEONFP() local
2558 __ fcmle(v24.V2S(), v31.V2S(), 0.0); in GenerateTestSequenceNEONFP() local
2559 __ fcmle(v8.V4S(), v23.V4S(), 0.0); in GenerateTestSequenceNEONFP() local
|
| D | test-simulator-aarch64.cc | 4354 DEFINE_TEST_NEON_2OPIMM_FCMP_ZERO(fcmle, Basic, Zero) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4398 DEFINE_TEST_NEON_2OPIMM_FP_SCALAR_SD(fcmle, Basic, Zero)
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 296 # CHECK: fcmle v11.2d, v6.2d, #0.0
1670 # CHECK: fcmle s10, s11, #0.0
1671 # CHECK: fcmle d20, d21, #0.0
|
| D | arm64-advsimd.txt | 541 # CHECK: fcmle.2s v0, v0, #0
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2514 void fcmle(const VRegister& vd, const VRegister& vn, double imm);
|
| D | macro-assembler-aarch64.h | 2349 V(fcmle, Fcmle) \ in NEON_2VREG_MACRO_LIST()
|
| D | assembler-aarch64.cc | 2631 void Assembler::fcmle(const VRegister& vd, const VRegister& vn, double value) { in fcmle() function in vixl::aarch64::Assembler
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1829 void fcmle(const VRegister& vd,
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 19873 fcmle v2.2d, v23.2d, #0 156bb1262e9ced5ecf0bc01379279ad4 102b48d571191b7343ffe07f6c71b9aa 00000…
19874 fcmle v2.4s, v23.4s, #0 816ee9c759ad1f781012efcd78644da0 1e0a3675967287524f0f875dfe515810 00000…
19875 fcmle v2.2s, v23.2s, #0 bd172b6befe14de21081b9a5a93d94fa 12383dc46894542323836fd5511584e3 00000…
|