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Searched refs:fp32 (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dhsa-fp-mode.ll65 attributes #2 = { nounwind "target-features"="-fp32-denormals,+fp64-denormals" }
66 attributes #3 = { nounwind "target-features"="+fp32-denormals,-fp64-denormals" }
67 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
68 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }
Ddefault-fp-mode.ll60 attributes #3 = { nounwind "target-features"="+fp32-denormals" }
61 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
62 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }
Dllvm.amdgcn.rcp.ll125 attributes #1 = { nounwind "unsafe-fp-math"="false" "target-features"="-fp32-denormals" }
126 attributes #2 = { nounwind "unsafe-fp-math"="true" "target-features"="-fp32-denormals" }
127 attributes #3 = { nounwind "unsafe-fp-math"="false" "target-features"="+fp32-denormals" }
128 attributes #4 = { nounwind "unsafe-fp-math"="true" "target-features"="+fp32-denormals" }
Drsq.ll1 ; RUN: llc -march=amdgcn -mattr=-fp32-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s |…
2 ; RUN: llc -march=amdgcn -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefi…
Dfcanonicalize.ll350 attributes #2 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }
351 attributes #3 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
Dfdiv.ll2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck …
Dmad-combine.ll8 ; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstr…
9 ; RUN: llc -march=amdgcn -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs…
/external/swiftshader/src/Common/
DHalf.cpp19 half::half(float fp32) in half() argument
21 unsigned int fp32i = *(unsigned int*)&fp32; in half()
/external/deqp/modules/gles2/accuracy/
Des2aVaryingInterpolationTests.cpp135 tcu::Float32 fp32(val); in isValidFloat() local
136 return !fp32.isDenorm() && !fp32.isInf() && !fp32.isNaN(); in isValidFloat()
/external/deqp/modules/gles3/accuracy/
Des3aVaryingInterpolationTests.cpp137 tcu::Float32 fp32(val); in isValidFloat() local
138 return !fp32.isDenorm() && !fp32.isInf() && !fp32.isNaN(); in isValidFloat()
/external/deqp/external/vulkancts/modules/vulkan/texture/
DvktTextureFilteringExplicitLodTests.cpp73 const tcu::FloatFormat fp32 (-126, 127, 23, true); in getConversionPrecision() local
102 return fp32; in getConversionPrecision()
106 return fp32; in getConversionPrecision()
115 const tcu::FloatFormat fp32 (-126, 127, 23, true); in getFilteringPrecision() local
144 return fp32; in getFilteringPrecision()
148 return fp32; in getFilteringPrecision()
/external/v8/gypfiles/
Dtoolchain.gypi476 ['mips_fpu_mode=="fp32"', {
542 ['mips_fpu_mode=="fp32"', {
593 ['mips_fpu_mode=="fp32"', {
677 ['mips_fpu_mode=="fp32"', {
756 ['mips_fpu_mode=="fp32"', {
813 ['mips_fpu_mode=="fp32"', {
Dstandalone.gypi446 # Possible values fp32, fp64, fpxx.
447 # fp32 - 32 32-bit FPU registers are available, doubles are placed in
450 # fpxx - compatibility mode, it chooses fp32 or fp64 depending on runtime
452 'mips_fpu_mode%': 'fp32',
/external/llvm/lib/Target/AMDGPU/
DAMDGPU.td175 // fp32 denormals also causes instructions to run at the double
177 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td263 // be used with fp32 as well. This could be done for fp128, in which
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td209 // Template for instructions which take three fp64 or fp32 args. The
213 // zero) variants for fp32 functions.
/external/v8/
DBUILD.gn281 } else if (mips_fpu_mode == "fp32") {
/external/arm-neon-tests/
Dref-rvct-neon.txt7864 VCVT FP16 (check fp16-fp32 inf/nan/denormal) output:
7867 VCVT FP16 (check fp32-fp16 inf/nan) output:
Dref-rvct-all.txt7864 VCVT FP16 (check fp16-fp32 inf/nan/denormal) output:
7867 VCVT FP16 (check fp32-fp16 inf/nan) output: