| /external/llvm/test/MC/Mips/msa/ |
| D | test_2rf.s | 19 # CHECK: frint.w $w7, $w15 # encoding: [0x7b,0x2c,0x79,0xde]
20 # CHECK: frint.d $w21, $w22 # encoding: [0x7b,0x2d,0xb5,0x5e]
52 frint.w $w7, $w15
53 frint.d $w21, $w22
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | 2rf.ll | 90 %1 = tail call <4 x float> @llvm.mips.frint.w(<4 x float> %0)
95 declare <4 x float> @llvm.mips.frint.w(<4 x float>) nounwind
100 ; CHECK-DAG: frint.w [[WD:\$w[0-9]+]], [[WS]]
111 %1 = tail call <2 x double> @llvm.mips.frint.d(<2 x double> %0)
116 declare <2 x double> @llvm.mips.frint.d(<2 x double>) nounwind
121 ; CHECK-DAG: frint.d [[WD:\$w[0-9]+]], [[WS]]
139 ; CHECK-DAG: frint.w [[WD:\$w[0-9]+]], [[WS]]
157 ; CHECK-DAG: frint.d [[WD:\$w[0-9]+]], [[WS]]
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 47 // WebAssembly doesn't expose inexact exceptions, so map frint to fnearbyint.
48 def : Pat<(frint f32:$src), (NEAREST_F32 f32:$src)>;
49 def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>;
|
| /external/llvm/test/MC/Disassembler/Mips/msa/ |
| D | test_2rf.txt | 19 0x7b 0x2c 0x79 0xde # CHECK: frint.w $w7, $w15
20 0x7b 0x2d 0xb5 0x5e # CHECK: frint.d $w21, $w22
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFP.td | 313 // frint rounds according to the current mode (modifier 0) and detects
315 def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
316 def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
317 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
326 // fnearbyint is like frint but does not detect inexact conditions.
|
| D | SystemZInstrVector.td | 796 def : FPConversion<insn, frint, tr, tr, 0, 0>;
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | invalid-msa.s | 33 …frint.d $w20,$w8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
34 …frint.w $w11,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
|
| /external/vixl/doc/ |
| D | changelog.md | 44 + Added support for all `frint` instruction variants.
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | CIInstructions.td | 45 VOP_F64_F64, frint
|
| D | R600Instructions.td | 744 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
|
| D | SIInstructions.td | 1300 VOP_F32_F32, frint
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 316 [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 2112 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2113 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 6480 def : Pat<(f32 (frint FR32:$src)),
6482 def : Pat<(f64 (frint FR64:$src)),
6497 def : Pat<(v4f32 (frint VR128:$src)),
6508 def : Pat<(v2f64 (frint VR128:$src)),
6519 def : Pat<(v8f32 (frint VR256:$src)),
6530 def : Pat<(v4f64 (frint VR256:$src)),
6556 def : Pat<(f32 (frint FR32:$src)),
6558 def : Pat<(f64 (frint FR64:$src)),
6571 def : Pat<(v4f32 (frint VR128:$src)),
6582 def : Pat<(v2f64 (frint VR128:$src)),
|
| D | X86InstrAVX512.td | 6221 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
6237 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
7284 def : Pat<(v16f32 (frint VR512:$src)),
7295 def : Pat<(v8f64 (frint VR512:$src)),
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 378 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 2706 frint(vform, rd, rn, fpcr_rounding, inexact_exception); in VisitFPDataProcessing1Source()
3245 frint(fpf, rd, rn, fpcr_rounding, inexact_exception); in VisitNEON2RegMisc()
|
| D | simulator-aarch64.h | 2834 LogicVRegister frint(VectorFormat vform,
|
| D | logic-aarch64.cc | 4431 LogicVRegister Simulator::frint(VectorFormat vform, in frint() function in vixl::aarch64::Simulator
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 448 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 905 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2594 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2841 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
|