| /external/llvm/test/MC/AArch64/ |
| D | neon-frsqrt-frecp.s | 8 frsqrts v0.4h, v31.4h, v16.4h
9 frsqrts v4.8h, v7.8h, v15.8h
10 frsqrts v0.2s, v31.2s, v16.2s
11 frsqrts v4.4s, v7.4s, v15.4s
12 frsqrts v29.2d, v2.2d, v5.2d
|
| D | neon-scalar-recip.s | 21 frsqrts h21, h5, h12
22 frsqrts s21, s5, s12
23 frsqrts d8, d22, d18 define
|
| D | fullfp16-neon-neg.s | 168 frsqrts v0.4h, v31.4h, v16.4h
170 frsqrts v4.8h, v7.8h, v15.8h
284 frsqrts h21, h5, h12
|
| D | arm64-advsimd.s | 332 frsqrts.2s v0, v0, v0
403 ; CHECK: frsqrts.2s v0, v0, v0 ; encoding: [0x00,0xfc,0xa0,0x0e]
465 frsqrts.4h v0, v0, v0
490 ; CHECK: frsqrts.4h v0, v0, v0 ; encoding: [0x00,0x3c,0xc0,0x0e]
515 frsqrts.8h v0, v0, v0
540 ; CHECK: frsqrts.8h v0, v0, v0 ; encoding: [0x00,0x3c,0xc0,0x4e]
|
| D | neon-diagnostics.s | 397 frsqrts v0.2d, v1.2d, v2.2s
398 frsqrts v0.4h, v1.4h, v2.4h
3903 frsqrts s21, h5, s12
3904 frsqrts d8, s22, d18 define
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsqrt.ll | 37 ;CHECK: frsqrts.2s
40 %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
46 ;CHECK: frsqrts.4s
49 %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
55 ;CHECK: frsqrts.2d
58 %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
62 declare <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
63 declare <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
64 declare <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double>, <2 x double>) nounwind readnone
217 ; CHECK: frsqrts s0, s0, s1
[all …]
|
| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 4008 LogicVRegister Simulator::frsqrts(VectorFormat vform, in frsqrts() function in vixl::aarch64::Simulator
4023 LogicVRegister Simulator::frsqrts(VectorFormat vform, in frsqrts() function in vixl::aarch64::Simulator
4028 frsqrts<float>(vform, dst, src1, src2); in frsqrts()
4031 frsqrts<double>(vform, dst, src1, src2); in frsqrts()
|
| D | simulator-aarch64.h | 2757 LogicVRegister frsqrts(VectorFormat vform,
2761 LogicVRegister frsqrts(VectorFormat vform,
|
| D | simulator-aarch64.cc | 3341 frsqrts(vf, rd, rn, rm); in VisitNEON3Same()
4633 frsqrts(vf, rd, rn, rm); in VisitNEONScalar3Same()
|
| D | assembler-aarch64.h | 2328 void frsqrts(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | macro-assembler-aarch64.h | 2154 V(frsqrts, Frsqrts) \
|
| D | assembler-aarch64.cc | 2729 V(frsqrts, NEON_FRSQRTS, NEON_FRSQRTS_scalar) \
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 498 0x~~~~~~~~~~~~~~~~ 5ef1ffa4 frsqrts d4, d29, d17
499 0x~~~~~~~~~~~~~~~~ 5eb8fc6e frsqrts s14, s3, s24
2366 0x~~~~~~~~~~~~~~~~ 4eefff99 frsqrts v25.2d, v28.2d, v15.2d
2367 0x~~~~~~~~~~~~~~~~ 0eaaff49 frsqrts v9.2s, v26.2s, v10.2s
2368 0x~~~~~~~~~~~~~~~~ 4eaafc25 frsqrts v5.4s, v1.4s, v10.4s
|
| D | log-disasm | 498 0x~~~~~~~~~~~~~~~~ 5ef1ffa4 frsqrts d4, d29, d17
499 0x~~~~~~~~~~~~~~~~ 5eb8fc6e frsqrts s14, s3, s24
2366 0x~~~~~~~~~~~~~~~~ 4eefff99 frsqrts v25.2d, v28.2d, v15.2d
2367 0x~~~~~~~~~~~~~~~~ 0eaaff49 frsqrts v9.2s, v26.2s, v10.2s
2368 0x~~~~~~~~~~~~~~~~ 4eaafc25 frsqrts v5.4s, v1.4s, v10.4s
|
| D | log-all | 1131 0x~~~~~~~~~~~~~~~~ 5ef1ffa4 frsqrts d4, d29, d17
1133 0x~~~~~~~~~~~~~~~~ 5eb8fc6e frsqrts s14, s3, s24
6035 0x~~~~~~~~~~~~~~~~ 4eefff99 frsqrts v25.2d, v28.2d, v15.2d
6037 0x~~~~~~~~~~~~~~~~ 0eaaff49 frsqrts v9.2s, v26.2s, v10.2s
6039 0x~~~~~~~~~~~~~~~~ 4eaafc25 frsqrts v5.4s, v1.4s, v10.4s
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 575 __ frsqrts(d4, d29, d17); in GenerateTestSequenceFP() local
576 __ frsqrts(s14, s3, s24); in GenerateTestSequenceFP() local
2718 __ frsqrts(v25.V2D(), v28.V2D(), v15.V2D()); in GenerateTestSequenceNEONFP() local
2719 __ frsqrts(v9.V2S(), v26.V2S(), v10.V2S()); in GenerateTestSequenceNEONFP() local
2720 __ frsqrts(v5.V4S(), v1.V4S(), v10.V4S()); in GenerateTestSequenceNEONFP() local
|
| D | test-simulator-aarch64.cc | 4110 DEFINE_TEST_NEON_3SAME_FP(frsqrts, Basic)
4168 DEFINE_TEST_NEON_3SAME_FP_SCALAR(frsqrts, Basic)
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 171 # CHECK: frsqrts v31.2d, v15.2d, v8.2d
1507 # CHECK: frsqrts s21, s5, s12
1508 # CHECK: frsqrts d8, d22, d18
|
| D | arm64-advsimd.txt | 315 # CHECK: frsqrts.2s v0, v0, v0
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 26673 frsqrts d2, d11, d29 3a6981d76589b8d982bd58214b7c40f0 99ec360eed34356ccb9b81f11b6ee3df eba76f51…
26674 frsqrts s2, s11, s29 582361c1915ca8e177744c423ad40a20 2ba325970917d9b9f0c9f32ffeb8d9f9 ab593df0…
26675 frsqrts v2.2d, v11.2d, v29.2d 09a1d547c7321eb28466909168184899 67cc4d3be6cc496d83209b5a16fcc83a …
26676 frsqrts v2.4s, v11.4s, v29.4s 527541dccb603f802ea90a00191d9d10 51fa136d46a6a9bc09b65e63a70e5558 …
26677 frsqrts v2.2s, v11.2s, v29.2s 363409f6613a2e7ef94f9c8592b6ad39 ecc0dba2effa1ed9069d1f3ff5c32305 …
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2470 void frsqrts(const VRegister& vd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2982 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>;
3262 defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts>;
|