| /external/swiftshader/third_party/LLVM/test/CodeGen/SPARC/ |
| D | 2008-10-10-InlineAsmMemoryOperand.ll | 9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
|
| /external/llvm/test/CodeGen/SPARC/ |
| D | 2008-10-10-InlineAsmMemoryOperand.ll | 9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
|
| /external/llvm/test/MC/Sparc/ |
| D | sparc-special-registers.s | 43 ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
44 ld [%g2 + 20],%fsr
46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
49 ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
50 st %fsr,[%g2 + 20]
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
|
| D | sparcv9-instructions.s | 95 ! V8-NEXT: ldx [%g2 + 20],%fsr
96 ! V9: ldx [%g2+20], %fsr ! encoding: [0xc3,0x08,0xa0,0x14]
97 ldx [%g2 + 20],%fsr
100 ! V8-NEXT: ldx [%g2 + %i5],%fsr
101 ! V9: ldx [%g2+%i5], %fsr ! encoding: [0xc3,0x08,0x80,0x1d]
102 ldx [%g2 + %i5],%fsr
105 ! V8-NEXT: stx %fsr,[%g2 + 20]
106 ! V9: stx %fsr, [%g2+20] ! encoding: [0xc3,0x28,0xa0,0x14]
107 stx %fsr,[%g2 + 20]
110 ! V8-NEXT: stx %fsr,[%g2 + %i5]
[all …]
|
| /external/google-breakpad/src/google_breakpad/common/ |
| D | minidump_cpu_sparc.h | 88 uint64_t fsr; /* FPU status register */ member
|
| /external/llvm/test/MC/Disassembler/Sparc/ |
| D | sparc-special-registers.txt | 36 # CHECK: st %fsr, [%i5]
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 51 fsr(src) in SrcRegister()
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { } in SrcRegister()
70 fsr(NULL) in SrcRegister()
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect; in isIndirect()
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index; in getIndex()
96 assert(fsr && isIndirect(dim)); in getIndirect()
98 return SrcRegister(fsr->DimIndirect); in getIndirect()
99 return SrcRegister(fsr->Indirect); in getIndirect()
112 const struct tgsi_full_src_register *fsr; member in tgsi::Instruction::SrcRegister
|
| /external/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_linux.cc | 1294 uptr fsr = ucontext->uc_mcontext.error_code; in GetWriteFlag() local
1298 if (fsr == 0) return UNKNOWN; in GetWriteFlag()
1299 return fsr & FSR_WRITE ? WRITE : READ; in GetWriteFlag()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 538 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
540 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
544 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
546 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
600 "st %fsr, [$addr]", [], IIC_st>;
602 "st %fsr, [$addr]", [], IIC_st>;
613 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
615 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
|
| /external/google-breakpad/src/processor/ |
| D | dump_context.cc | 502 context_sparc->float_save.fsr); in Print()
|
| D | minidump.cc | 962 Swap(&context_sparc->float_save.fsr); in Read()
|
| /external/elfutils/tests/ |
| D | run-allregs.sh | 2421 70: %fsr (fsr), unsigned 32 bits
2512 83: %fsr (fsr), unsigned 64 bits
|