| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 687 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in SoftenSetCCOperands()
690 NewRHS, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); in SoftenSetCCOperands()
726 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
769 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
787 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
906 DAG.getCondCode(ISD::SETEQ)); in ExpandFloatRes_FABS()
1231 Lo, Hi, DAG.getCondCode(ISD::SETLT)); in ExpandFloatRes_XINT_TO_FP()
1337 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1396 DAG.getCondCode(ISD::SETGE)); in ExpandFloatOp_FP_TO_UINT()
1419 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
[all …]
|
| D | LegalizeIntegerTypes.cpp | 2538 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2582 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
2601 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
2618 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
|
| D | LegalizeDAG.cpp | 3748 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3786 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3804 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
|
| D | SelectionDAG.cpp | 1217 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 438 SDValue getCondCode(ISD::CondCode Cond);
571 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
580 LHS, RHS, True, False, getCondCode(Cond));
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1064 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1147 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
1153 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1181 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1189 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1221 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1247 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 881 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
934 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
956 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
1578 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1674 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1691 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
|
| D | LegalizeIntegerTypes.cpp | 2866 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2920 LHSHi, RHSHi, LowCmp.getValue(1), DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2951 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
2970 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
2987 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
|
| D | LegalizeDAG.cpp | 1583 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1634 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3538 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3652 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3683 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
|
| D | TargetLowering.cpp | 267 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in softenSetCCOperands()
273 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); in softenSetCCOperands()
|
| D | SelectionDAG.cpp | 1455 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 625 SDValue getCondCode(ISD::CondCode Cond);
821 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
842 LHS, RHS, True, False, getCondCode(Cond));
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 450 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon92cf716e0311::ARMOperand
928 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addCondCodeOperands()
929 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
955 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addITCondCodeOperands()
1676 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 354 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon26fd99540211::AArch64Operand
1279 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
1800 OS << "<condcode " << getCondCode() << ">"; in print()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 603 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonef5d38c20311::ARMOperand
1761 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1762 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
1788 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2883 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
4797 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
|