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Searched refs:getReg (Results 1 – 25 of 553) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
DX86InstComments.cpp37 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
43 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
44 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
50 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
58 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
64 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
67 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
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DX86ATTInstPrinter.cpp94 O << '%' << getRegisterName(Op.getReg()); in printOperand()
116 if (SegReg.getReg()) { in printMemReference()
123 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
130 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
132 if (BaseReg.getReg()) in printMemReference()
135 if (IndexReg.getReg()) { in printMemReference()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
281 MaskRegName = getRegName(MI->getOperand(1).getReg()); in getMaskName()
345 MaskRegName = getRegName(MI->getOperand(2).getReg()); in getMaskName()
384 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
393 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
394 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
400 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
409 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
410 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
416 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
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/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp101 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
102 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
107 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()
109 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
110 IsVRReg(SrcMO.getReg(), MRI) || in processBlock()
111 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
112 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
121 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()
126 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
127 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
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DPPCMIPeephole.cpp121 unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg()); in simplifyCode()
122 unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg()); in simplifyCode()
133 = lookThruCopyLike(DefMI->getOperand(1).getReg()); in simplifyCode()
135 = lookThruCopyLike(DefMI->getOperand(2).getReg()); in simplifyCode()
143 TII->get(PPC::COPY), MI.getOperand(0).getReg()) in simplifyCode()
156 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
157 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
168 TII->get(PPC::COPY), MI.getOperand(0).getReg()) in simplifyCode()
209 CopySrcReg = MI->getOperand(1).getReg(); in lookThruCopyLike()
212 CopySrcReg = MI->getOperand(2).getReg(); in lookThruCopyLike()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp69 O << '\t' << getRegisterName(Dst.getReg()) in printInst()
70 << ", " << getRegisterName(MO1.getReg()); in printInst()
72 O << ", " << getRegisterName(MO2.getReg()); in printInst()
88 O << '\t' << getRegisterName(Dst.getReg()) in printInst()
89 << ", " << getRegisterName(MO1.getReg()); in printInst()
104 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
118 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}"; in printInst()
125 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
135 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp90 printRegName(O, Dst.getReg()); in printInst()
92 printRegName(O, MO1.getReg()); in printInst()
95 printRegName(O, MO2.getReg()); in printInst()
112 printRegName(O, Dst.getReg()); in printInst()
114 printRegName(O, MO1.getReg()); in printInst()
130 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
144 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
149 printRegName(O, MI->getOperand(1).getReg()); in printInst()
159 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
173 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp189 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
190 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
207 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
208 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
228 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
229 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
238 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
239 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
248 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
249 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/external/llvm/lib/CodeGen/
DImplicitNullChecks.cpp204 if (!MO.isReg() || !MO.getReg()) in rememberInstruction()
208 auto It = RegDefs.find(MO.getReg()); in rememberInstruction()
210 RegDefs.insert({MO.getReg(), MI}); in rememberInstruction()
216 RegUses.insert(MO.getReg()); in rememberInstruction()
232 if (MO.isReg() && MO.getReg()) { in isSafeToHoist()
236 if (!TRI.regsOverlap(Reg, MO.getReg())) in isSafeToHoist()
262 if (!MO.isReg() || !MO.getReg()) in isSafeToHoist()
266 assert((!MO.isDef() || RegDefs.count(MO.getReg())) && in isSafeToHoist()
268 return !MO.isDef() || RegDefs.find(MO.getReg())->second == MI; in isSafeToHoist()
284 if (TRI.regsOverlap(Reg, MO.getReg())) in isSafeToHoist()
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DTwoAddressInstructionPass.cpp205 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
209 UseRegs.insert(MO.getReg()); in sink3AddrInstruction()
218 DefReg = MO.getReg(); in sink3AddrInstruction()
274 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
344 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain()
385 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
386 SrcReg = MI.getOperand(1).getReg(); in isCopyToReg()
388 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
389 SrcReg = MI.getOperand(2).getReg(); in isCopyToReg()
478 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
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/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp190 unsigned R = Op.getReg(); in isFixedInstr()
239 unsigned T = MO.getReg(); in partitionRegisters()
397 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
456 unsigned PR = Cond[1].getReg(); in collectIndRegsForLoop()
464 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
491 unsigned R = MD.getReg(); in collectIndRegsForLoop()
507 unsigned T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
560 unsigned R = Op.getReg(); in createHalfInstr()
601 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg()); in splitMemRef()
608 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
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DHexagonPeephole.cpp142 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
143 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
163 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
164 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
180 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
181 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction()
191 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
192 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
214 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
215 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
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DHexagonVLIWPacketizer.cpp120 unsigned R = MO.getReg(); in hasWriteToReadDep()
286 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) in isCallDependent()
354 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
394 unsigned DestReg = MI->getOperand(0).getReg(); in canPromoteToDotCur()
397 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
464 DefRegsSet.insert(MO.getReg()); in getPostIncrementOperand()
467 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
538 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
560 getPostIncrementOperand(MI, HII).getReg() == DepReg) { in canPromoteToNewValueStore()
565 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) { in canPromoteToNewValueStore()
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/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp106 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
274 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) in getEquivalentCompactForm()
290 (I->getOperand(0).getReg() == Mips::ZERO || in getEquivalentCompactForm()
291 I->getOperand(0).getReg() == Mips::ZERO_64)) && in getEquivalentCompactForm()
293 (I->getOperand(1).getReg() == Mips::ZERO || in getEquivalentCompactForm()
294 I->getOperand(1).getReg() == Mips::ZERO_64))) in getEquivalentCompactForm()
306 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) in getEquivalentCompactForm()
312 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) in getEquivalentCompactForm()
316 if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) in getEquivalentCompactForm()
320 if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) in getEquivalentCompactForm()
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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp536 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { in getReg() function
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
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/external/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp74 if (TargetRegisterInfo::isVirtualRegister(MO->getReg())) in isVGPR()
75 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg())); in isVGPR()
77 return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg())); in isVGPR()
154 if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) { in foldImmediates()
155 unsigned Reg = Src0.getReg(); in foldImmediates()
185 if (Use.getReg() == AMDGPU::VCC) { in copyFlagsToImplicitVCC()
228 TargetRegisterInfo::isPhysicalRegister(MI.getOperand(0).getReg())) { in runOnMachineFunction()
282 if (TargetRegisterInfo::isVirtualRegister(Dest.getReg()) && in runOnMachineFunction()
284 MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg()); in runOnMachineFunction()
288 if (Src0.isReg() && Src0.getReg() == Dest.getReg()) { in runOnMachineFunction()
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DSIFixSGPRCopies.cpp119 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg())) in hasVGPROperands()
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
132 unsigned DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses()
133 unsigned SrcReg = Copy.getOperand(1).getReg(); in getCopyRegClasses()
182 unsigned DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence()
214 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg()); in foldVGPRCopyIntoRegSequence()
217 unsigned SrcReg = MI.getOperand(I).getReg(); in foldVGPRCopyIntoRegSequence()
261 if (!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg())) in runOnMachineFunction()
275 unsigned Reg = MI.getOperand(0).getReg(); in runOnMachineFunction()
318 unsigned Reg = MI.getOperand(i).getReg(); in runOnMachineFunction()
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DR600ExpandSpecialInstrs.cpp87 DstOp.getReg(), AMDGPU::OQAP); in runOnMachineFunction()
95 MI.getOperand(LDSPredSelIdx).getReg()); in runOnMachineFunction()
107 MI.getOperand(0).getReg(), // dst in runOnMachineFunction()
108 MI.getOperand(1).getReg(), // src0 in runOnMachineFunction()
129 DstReg = MI.getOperand(Chan).getReg(); in runOnMachineFunction()
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
160 DstReg = MI.getOperand(Chan-2).getReg(); in runOnMachineFunction()
163 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
183 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction()
202 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction()
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DSILowerControlFlow.cpp251 unsigned Reg = MI.getOperand(0).getReg(); in If()
252 unsigned Vcc = MI.getOperand(1).getReg(); in If()
274 unsigned Dst = MI.getOperand(0).getReg(); in Else()
275 unsigned Src = MI.getOperand(1).getReg(); in Else()
308 unsigned Dst = MI.getOperand(0).getReg(); in Break()
309 unsigned Src = MI.getOperand(1).getReg(); in Break()
322 unsigned Dst = MI.getOperand(0).getReg(); in IfBreak()
323 unsigned Vcc = MI.getOperand(1).getReg(); in IfBreak()
324 unsigned Src = MI.getOperand(2).getReg(); in IfBreak()
337 unsigned Dst = MI.getOperand(0).getReg(); in ElseBreak()
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DSILowerI1Copies.cpp85 unsigned Reg = MI.getOperand(0).getReg(); in runOnMachineFunction()
98 if (!TargetRegisterInfo::isVirtualRegister(Src.getReg()) || in runOnMachineFunction()
99 !TargetRegisterInfo::isVirtualRegister(Dst.getReg())) in runOnMachineFunction()
102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction()
103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction()
107 I1Defs.push_back(Dst.getReg()); in runOnMachineFunction()
110 MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg()); in runOnMachineFunction()
113 I1Defs.push_back(Dst.getReg()); in runOnMachineFunction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp50 return X86_MC::getX86RegNum(MO.getReg()); in GetX86RegNum()
64 unsigned SrcReg = MI.getOperand(OpNum).getReg(); in getVEXRegisterEncoding()
165 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
166 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
167 (IndexReg.getReg() != 0 && in Is32BitMemOperand()
168 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
250 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte()
255 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); in EmitMemModRMByte()
286 IndexReg.getReg() == 0 && in EmitMemModRMByte()
325 assert(IndexReg.getReg() != X86::ESP && in EmitMemModRMByte()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DProcessImplicitDefs.cpp54 ImpDefRegs.count(MI->getOperand(0).getReg())); in CanTurnIntoImplicitDef()
57 ImpDefRegs.count(MI->getOperand(0).getReg())); in CanTurnIntoImplicitDef()
67 if (MO1.getReg() != Reg) in isUndefCopy()
69 if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg())) in isUndefCopy()
110 unsigned Reg = MI->getOperand(0).getReg(); in runOnMachineFunction()
123 if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) { in runOnMachineFunction()
125 LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg()); in runOnMachineFunction()
128 unsigned Reg = MI->getOperand(0).getReg(); in runOnMachineFunction()
145 unsigned Reg = MO.getReg(); in runOnMachineFunction()
178 if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg) in runOnMachineFunction()
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DTwoAddressInstructionPass.cpp196 unsigned MOReg = MO.getReg(); in Sink3AddrInstruction()
200 UseRegs.insert(MO.getReg()); in Sink3AddrInstruction()
209 DefReg = MO.getReg(); in Sink3AddrInstruction()
254 unsigned MOReg = MO.getReg(); in Sink3AddrInstruction()
294 if (MO.isReg() && MO.getReg() == Reg && in isTwoAddrUse()
398 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
399 SrcReg = MI.getOperand(1).getReg(); in isCopyToReg()
401 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
402 SrcReg = MI.getOperand(2).getReg(); in isCopyToReg()
459 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
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/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp139 unsigned Reg = MO.getReg(); in usesRegClass()
169 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
198 unsigned Reg = MO.getReg(); in eraseInstrWithNoUses()
221 unsigned DefReg = MODef.getReg(); in eraseInstrWithNoUses()
251 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg()); in optimizeSDPattern()
255 unsigned DPRReg = MI->getOperand(1).getReg(); in optimizeSDPattern()
256 unsigned SPRReg = MI->getOperand(2).getReg(); in optimizeSDPattern()
259 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern()
260 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern()
277 unsigned FullReg = SPRMI->getOperand(1).getReg(); in optimizeSDPattern()
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