Searched refs:hasV6T2Ops (Results 1 – 19 of 19) sorted by relevance
192 bool hasV6T2Ops() const { return HasV6T2Ops; } in hasV6T2Ops() function241 bool useMovt() const { return UseMovt && hasV6T2Ops(); } in useMovt()
113 UseMovt = hasV6T2Ops(); in ARMSubtarget()116 UseMovt = DarwinUseMOVT && hasV6T2Ops(); in ARMSubtarget()
2045 if (!Subtarget->hasV6T2Ops()) in SelectV6T2BitfieldExtractOp()2166 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) { in SelectT2CMOVImmOp()2193 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) { in SelectARMCMOVImmOp()2199 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) { in SelectARMCMOVImmOp()2529 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); in Select()
901 if (Subtarget->hasV6T2Ops()) in emitPseudoInstruction()
655 if (!STI->hasV6T2Ops() && in ExpandMOV32BitImm()
552 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) { in ARMMaterializeInt()
177 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,179 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;219 // FIXME: Eventually this will be just "hasV6T2Ops".513 if (Subtarget->hasV6T2Ops())
738 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) in ARMTargetLowering()3350 if (!ST->hasV6T2Ops()) in LowerCTTZ()6771 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) in PerformORCombine()8588 if (Subtarget->hasV6T2Ops()) in LowerAsmOperandForConstraint()
144 assert(hasV6T2Ops() || !hasThumb2()); in initSubtargetFeatures()
479 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { in ARMMaterializeInt()491 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { in ARMMaterializeInt()835 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 && in ARMSimplifyAddress()931 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) in ARMEmitLoad()950 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) in ARMEmitLoad()965 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) in ARMEmitLoad()1076 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) in ARMEmitStore()1089 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) in ARMEmitStore()1103 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) in ARMEmitStore()
32 return ST->hasV6T2Ops() ? 2 : 3; in getIntImmCost()39 return ST->hasV6T2Ops() ? 2 : 3; in getIntImmCost()
399 bool hasV6T2Ops() const { return HasV6T2Ops; } in hasV6T2Ops() function
336 if (!Subtarget->hasV6T2Ops()) in PreprocessISelDAG()478 if (Subtarget->hasV6T2Ops() && Val <= 0xffff) return 1; // MOVW in ConstantMaterializationCost()485 if (Subtarget->hasV6T2Ops() && Val <= 0xffff) return 1; // MOVW in ConstantMaterializationCost()2330 if (!Subtarget->hasV6T2Ops()) in tryV6T2BitfieldExtractOp()2866 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); in Select()
575 return (Subtarget->hasV8MBaselineOps() && !Subtarget->hasV6T2Ops()) || in isV8M()599 } else if (Subtarget->hasV6T2Ops()) in getArchForCPU()
750 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) in ARMTargetLowering()4682 if (!ST->hasV6T2Ops()) in LowerCTTZ()7638 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) { in EmitSjLjDispatchBlock()9347 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) in PerformORCombine()10963 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) { in PerformCMOVCombine()11872 if (Subtarget->hasV6T2Ops()) in LowerAsmOperandForConstraint()12481 return Subtarget->hasV6T2Ops(); in isCheapToSpeculateCttz()12485 return Subtarget->hasV6T2Ops(); in isCheapToSpeculateCtlz()
241 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops(); in emitAligningInstructions()
677 if (!STI->hasV6T2Ops() && in ExpandMOV32BitImm()
206 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,208 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;301 // FIXME: Eventually this will be just "hasV6T2Ops".
266 bool hasV6T2Ops() const { in hasV6T2Ops() function in __anonef5d38c20111::ARMAsmParser6956 else if (hasV6T2Ops() && in processInstruction()